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fa41668e
Commit
fa41668e
authored
Jul 26, 2013
by
Matthieu Cattin
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fmc_adc_spec, test30: Add software reset methods, add sw reset test, add sw reset register.
parent
b4ec16ba
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3 changed files
with
304 additions
and
1 deletion
+304
-1
fmc_adc_spec.py
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
+26
-0
spec_carrier_csr.py
test/fmcadc100m14b4cha/python/spec_carrier_csr.py
+4
-1
test30.py
test/fmcadc100m14b4cha/python/test30.py
+274
-0
No files found.
test/fmcadc100m14b4cha/python/fmc_adc_spec.py
View file @
fa41668e
...
...
@@ -86,6 +86,9 @@ class CFmcAdc100mSpec:
if
(
ct
==
0xFFFFFFFF
):
raise
FmcAdc100mSpecOperationError
(
"Bitstream not properly loaded."
)
# Release the mezzanine software reset
self
.
set_sw_rst
(
1
)
# TODO
# Check if the expected bitstream loaded
#bs = self.get_bitstream_type()
...
...
@@ -175,6 +178,29 @@ class CFmcAdc100mSpec:
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Mezzanine software reset
def
sw_rst
(
self
):
try
:
self
.
csr
.
set_field
(
'RST'
,
'FMC0'
,
0
)
time
.
sleep
(
0.001
)
self
.
csr
.
set_field
(
'RST'
,
'FMC0'
,
1
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Set mezzanine software reset state
def
set_sw_rst
(
self
,
value
):
try
:
return
self
.
csr
.
set_field
(
'RST'
,
'FMC0'
,
value
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
# Get mezzanine software reset state
def
get_sw_rst
(
self
):
try
:
return
self
.
csr
.
get_field
(
'RST'
,
'FMC0'
)
except
CSRDeviceOperationError
as
e
:
raise
FmcAdc100mSpecOperationError
(
e
)
#======================================================================
# Onewire thermometer and unique ID
...
...
test/fmcadc100m14b4cha/python/spec_carrier_csr.py
View file @
fa41668e
...
...
@@ -24,5 +24,8 @@ CARRIER_CSR=['Carrier control and status registers',{
'LED_GREEN'
:[
0
,
'Green LED'
,
0x1
],
'LED_RED'
:[
1
,
'Red LED'
,
0x1
],
'DAC_CLR_N'
:[
2
,
'VCXO DAC clear (active low)'
,
0x1
],
'RESERVED'
:[
3
,
'Reserved'
,
0x1FFFFFFF
]}]
'RESERVED'
:[
3
,
'Reserved'
,
0x1FFFFFFF
]}],
'RST'
:[
0x0C
,
'Reset'
,
{
'FMC0'
:[
0
,
'FMC 1 software reset'
,
0x1
],
'RESERVED'
:[
1
,
'Reserved'
,
0x7FFFFFFF
]}]
}]
test/fmcadc100m14b4cha/python/test30.py
0 → 100755
View file @
fa41668e
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2011
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 30/5/2012
# Import system modules
import
sys
import
time
import
os
# Add common modules and libraries location to path
sys
.
path
.
append
(
'../../../'
)
sys
.
path
.
append
(
'../../../gnurabbit/python/'
)
sys
.
path
.
append
(
'../../../common/'
)
# Import common modules
from
ptsexcept
import
*
import
rr
# Import specific modules
from
fmc_adc_spec
import
*
from
fmc_adc
import
*
from
numpy
import
*
from
pylab
import
*
from
calibr_box
import
*
import
find_usb_tty
from
PAGE.Agilent33250A
import
*
from
PAGE.SineWaveform
import
*
"""
test30: Test software reset.
Note: Requires test00.py to run first to load the firmware!
"""
NB_CHANNELS
=
4
AWG_SET_SLEEP
=
0.3
SSR_SET_SLEEP
=
0.05
BOX_SET_SLEEP
=
0.01
ACQ_TIMEOUT
=
10
PRE_TRIG_SAMPLES
=
10
POST_TRIG_SAMPLES
=
10000
NB_SHOTS
=
1
ACQ_LENGTH
=
10000
# in samples
def
open_all_channels
(
fmc
):
for
i
in
range
(
1
,
NB_CHANNELS
+
1
):
fmc
.
set_input_range
(
i
,
'OPEN'
)
time
.
sleep
(
SSR_SET_SLEEP
)
def
fmc_adc_init
(
spec
,
fmc
):
print
"Initialise FMC board.
\n
"
# Reset offset DACs
fmc
.
dc_offset_reset
()
# Make sure all switches are OFF
open_all_channels
(
fmc
)
# Set software trigger
fmc
.
set_soft_trig
()
# Set acquisition
fmc
.
set_pre_trig_samples
(
PRE_TRIG_SAMPLES
)
fmc
.
set_post_trig_samples
(
POST_TRIG_SAMPLES
)
fmc
.
set_shots
(
NB_SHOTS
)
# Converts two's complement hex to signed
def
hex2signed
(
value
):
if
(
value
&
0x8000
):
return
-
((
~
value
&
0xFFFF
)
+
1
)
else
:
return
value
# Converts digital value to volts
def
digital2volt
(
value
,
full_scale
,
nb_bit
):
return
float
(
value
)
*
float
(
full_scale
)
/
2
**
nb_bit
def
acq_channels
(
fmc
,
carrier
,
adc_fs
,
pause
):
# Make sure no acquisition is running
fmc
.
stop_acq
()
time
.
sleep
(
pause
)
# Start acquisition
fmc
.
start_acq
()
time
.
sleep
(
pause
)
# Trigger
fmc
.
sw_trig
()
# Wait end of acquisition
timeout
=
0
while
(
'IDLE'
!=
fmc
.
get_acq_fsm_state
()):
time
.
sleep
(
.1
)
timeout
+=
1
if
(
ACQ_TIMEOUT
<
timeout
):
print
"Acquisition timeout. Missing trigger?."
print
"Acq FSm state:
%
s"
%
fmc
.
get_acq_fsm_state
()
return
1
# Retrieve data trough DMA
trig_pos
=
fmc
.
get_trig_pos
()
# Enable "DMA done" iinterrupt
carrier
.
set_irq_en_mask
(
0x1
)
# Read ACQ_LENGTH samples after the trigger for all channels
channels_data
=
carrier
.
get_data
((
trig_pos
<<
3
),
ACQ_LENGTH
*
8
)
# Disable "DMA done" iinterrupt
carrier
.
set_irq_en_mask
(
0x0
)
channels_data
=
[
hex2signed
(
item
)
for
item
in
channels_data
]
channels_data
=
[
digital2volt
(
item
,
adc_fs
,
16
)
for
item
in
channels_data
]
return
channels_data
def
plot_channels
(
ch_data
,
ch_mean
,
ylimit
):
sample
=
arange
(
len
(
ch_data
[
0
]))
plot
(
sample
,
ch_data
[
0
],
'b'
,
label
=
'Channel 1'
)
plot
(
sample
,
ch_data
[
1
],
'g'
,
label
=
'Channel 2'
)
plot
(
sample
,
ch_data
[
2
],
'm'
,
label
=
'Channel 3'
)
plot
(
sample
,
ch_data
[
3
],
'c'
,
label
=
'Channel 4'
)
plot
(
sample
,
[
ch_mean
[
0
]]
*
len
(
sample
),
'r'
)
plot
(
sample
,
[
ch_mean
[
1
]]
*
len
(
sample
),
'r'
)
plot
(
sample
,
[
ch_mean
[
2
]]
*
len
(
sample
),
'r'
)
plot
(
sample
,
[
ch_mean
[
3
]]
*
len
(
sample
),
'r'
)
ylim
(
-
ylimit
-
(
ylimit
/
10.0
),
ylimit
+
(
ylimit
/
10.0
))
grid
(
color
=
'k'
,
linestyle
=
'--'
,
linewidth
=
1
)
legend
(
loc
=
'upper left'
)
show
()
return
0
def
main
(
default_directory
=
'.'
):
# Constants declaration
TEST_NB
=
30
FMC_ADC_BITSTREAM
=
'../firmwares/spec_fmcadc100m14b4cha.bin'
FMC_ADC_BITSTREAM
=
os
.
path
.
join
(
default_directory
,
FMC_ADC_BITSTREAM
)
EXPECTED_BITSTREAM_TYPE
=
0x1
# Calibration box vendor and product IDs
BOX_USB_VENDOR_ID
=
0x10c4
# Cygnal Integrated Products, Inc.
BOX_USB_PRODUCT_ID
=
0xea60
# CP210x Composite Device
# Agilent AWG serial access vendor and product IDs
AWG_USB_VENDOR_ID
=
0x0403
# Future Technology Devices International, Ltd
AWG_USB_PRODUCT_ID
=
0x6001
# FT232 USB-Serial (UART) IC
AWG_BAUD
=
57600
start_test_time
=
time
.
time
()
print
"================================================================================"
print
"Test
%02
d start
\n
"
%
TEST_NB
# SPEC object declaration
print
"Loading hardware access library and opening device.
\n
"
spec
=
rr
.
Gennum
()
# Load FMC ADC firmware
print
"Loading FMC ADC firmware:
%
s
\n
"
%
FMC_ADC_BITSTREAM
spec
.
load_firmware
(
FMC_ADC_BITSTREAM
)
time
.
sleep
(
2
)
# Carrier object declaration (SPEC board specific part)
# Used to check that the firmware is loaded.
try
:
carrier
=
CFmcAdc100mSpec
(
spec
,
EXPECTED_BITSTREAM_TYPE
)
except
FmcAdc100mSpecOperationError
as
e
:
raise
PtsCritical
(
"Carrier init failed, test stopped:
%
s"
%
e
)
# Mezzanine object declaration (FmcAdc100m14b4cha board specific part)
try
:
fmc
=
CFmcAdc100m
(
spec
)
except
FmcAdc100mOperationError
as
e
:
raise
PtsCritical
(
"Mezzanine init failed, test stopped:
%
s"
%
e
)
try
:
# Others objects declaration
usb_tty
=
find_usb_tty
.
CttyUSB
()
awg_tty
=
usb_tty
.
find_usb_tty
(
AWG_USB_VENDOR_ID
,
AWG_USB_PRODUCT_ID
)
box_tty
=
usb_tty
.
find_usb_tty
(
BOX_USB_VENDOR_ID
,
BOX_USB_PRODUCT_ID
)
gen
=
Agilent33250A
(
device
=
awg_tty
[
0
],
bauds
=
AWG_BAUD
)
sine
=
SineWaveform
()
box
=
CCalibr_box
(
box_tty
[
0
])
# Initialise fmc adc
fmc_adc_init
(
spec
,
fmc
)
# Use test data instead of data from ADC
# fmc.test_data_en()
# Use data pattern instead of ADC data
# fmc.testpat_en(0x2000)
# Acquisition parameters
ACQ_PAUSE
=
1
# pause between acq. stop and start, start and trigger
IN_RANGE
=
'100mV'
IN_TERM
=
'ON'
ADC_FS
=
{
'10V'
:
10.0
,
'1V'
:
1.0
,
'100mV'
:
0.1
}
# Set sine params
sine
.
frequency
=
1E6
sine
.
amplitude
=
0.8
*
ADC_FS
[
IN_RANGE
]
sine
.
dc
=
0
print
"
\n
Sine frequency:
%3.3
fMHz amplitude:
%2.3
fVp offset:
%2.3
fV"
%
(
sine
.
frequency
/
1E6
,
sine
.
amplitude
,
sine
.
dc
)
# Set AWG
gen
.
connect
()
gen
.
play
(
sine
)
gen
.
output
=
True
time
.
sleep
(
AWG_SET_SLEEP
)
# Make sure no acquisition is running
fmc
.
stop_acq
()
# Start acquisition
fmc
.
start_acq
()
print
(
'
\n
Should be in acquisition'
)
time
.
sleep
(
3
)
print
(
'
\n
FMC 1 software reset state: 0x
%.1
X'
%
carrier
.
get_sw_rst
())
print
(
'Resetting mezzanine'
)
carrier
.
sw_rst
()
print
(
'FMC 1 software reset state: 0x
%.1
X'
%
carrier
.
get_sw_rst
())
print
(
'Re-init the mezzanine'
)
fmc
.
__init__
(
spec
)
fmc_adc_init
(
spec
,
fmc
)
time
.
sleep
(
3
)
print
(
'Make a compete acquisition'
)
ch_mean
=
[]
channels_data
=
[]
for
ch
in
range
(
NB_CHANNELS
):
# Configure analogue input
fmc
.
set_input_range
(
ch
+
1
,
IN_RANGE
)
fmc
.
set_input_term
(
ch
+
1
,
IN_TERM
)
time
.
sleep
(
SSR_SET_SLEEP
)
# connect AWG to current channel
box
.
select_output_ch
(
ch
+
1
)
time
.
sleep
(
BOX_SET_SLEEP
)
# Perform an acquisition
acq_data
=
acq_channels
(
fmc
,
carrier
,
ADC_FS
[
IN_RANGE
],
ACQ_PAUSE
)
channels_data
.
append
(
acq_data
[
ch
::
4
])
ch_mean
.
append
(
mean
(
channels_data
[
ch
]))
# Plot all channels
plot_channels
(
channels_data
,
ch_mean
,
(
ADC_FS
[
IN_RANGE
]
/
2
))
# Make sure all switches are OFF
open_all_channels
(
fmc
)
# Switch AWG OFF
gen
.
output
=
False
gen
.
close
()
# Check if an error occured during frequency response test
# if(error != 0):
# raise PtsError('An error occured, check log for details.')
except
(
FmcAdc100mSpecOperationError
,
FmcAdc100mOperationError
,
CalibrBoxOperationError
)
as
e
:
raise
PtsError
(
"Test failed:
%
s"
%
e
)
print
""
print
"==> End of test
%02
d"
%
TEST_NB
print
"================================================================================"
end_test_time
=
time
.
time
()
print
"Test
%02
d elapsed time:
%.2
f seconds
\n
"
%
(
TEST_NB
,
end_test_time
-
start_test_time
)
if
__name__
==
'__main__'
:
main
()
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