Design Review 21/06/2016
26 June 2016, 16h - 17h, 774-1-014
Present
Serrano Javier (BE/CO), Bouhired-Ferrag Denia (BE/CO), Daniluk Grzegorz (BE/CO), Van der Bij Erik (BE/CO), Lampridis Dimitrios (BE/CO), Gousiou Evangelia (BE/CO)
Detailed comments on schematics
Top Level Sheet
- The inputs on the lower level hierarchical sheet should be placed on the right. The outputs on the left.
ADC sheet
- Remove the comment about the issue about the bandwidth which has been solved
Power Supplies, part 1
- “Double rectifier bridge to have the right polarity in each cases”. -> in all cases / in all supply configurations
- Remove the "Broches" which is in french and replace it by "pins"
- Put a comment to say where the heatsink has to be placed
Power Supplies, part 2
- U5 pin 1 not connected with a blob to P3V3.
- Double transistor in a single housing rather special, I assume. Better to have two separate ones.
Miscellaneous
- DS18B20U+ is also a unique ID IC.
- Add a flip flop to one output to reduce the FPGA output jitter. This flip flop has to be clocked by the sampling clock to be sure that the output will be synchronized with it.
Clock Input
- “Place 0 ohm close to the track to avoid creating a stub”. Not clear as instruction.
- Some components should not be mounted. Mark in schematics and in BOM. (e.g. R33)