Improvements after first design review
Following the design and layout review, we were lead to put some modifications on the design. Here is explained how we handled the different remarks.
Detailed comments on schematics
General remarks
- Avoid crossing the wires (use labels)
- Done
- OHL text in all corners of the pages. Put it on all pages in the
same place.
- Done
- Each symbol should be the precise order number. Now clock splitter
is only in a note that should use -1 version
- Done
- Add a thermometer to be able to control the temperature influence
- Done. Is there any pieces of VHDL code for the DS1BB20U+ ?
Sheet 1 : ADC Board
- Avoid using the bus connections on the main hierarchical page. It is
better to make them on the sub-page and then to route the bus on the
main page. That makes the connections easier to read.
- Done
- Put connectors on that page
- Done. Only for the "analog" inputs. Not for the power supply inputs
Sheet 2: Power supplies
- Add the nominal current at the input
- Done. Would probably be around 1A-1.5A depending on the microZed and the number of input used.
- Capacitors marked Cin1-Cin11 and Cout1-Cout10. Number normally (C1
etc). Same for Rset1, Cbias1 etc.
- Done
- Comment Vout (MAX) = -> Vout =, should remove the "MAX" or should
be a min value also
- Done, for further informations see the "Realisation of a low noise acquisition board : design choices"
- Specify PGFP = IN: “power good and fast start-up functionalities are
not needed”
- Will be taken into account for the next design
- How are heatsinks fixed?
- This application note gives some indications about the heatsink footprint
- Put a figure of the used heatsink on the schematic
- Done
- Put a comment on for the two bridges
- Done
- Use symbol of Schottky diodes, while likely use normal ones.
- According to us it is already the symbol of the Schottky diodes
- Specify Diodes used.
- Already in the detailed schematics PDF. Will be put in the not detailed schematics PDF for the next design
Sheet 3 & 4: ADC and inputs
- Add TVS on all inputs
- We have not found a TVS with a capacitance low enougth, we will rely on the diodes inside the ADC
- As the input are always the same circuit, make an hierarchical page
for them.
- Will be taken into account for the next schematic
- What is the signalling rate of the ADC digital output? Mention in
comment on schematics page. Is that compatible to the max rate of
the MicroZED?
- Unfortunately, with the new ADC, the sampling rate must be bellow 118 MHz to be compatible with the rate of MicroZed. This is the worst-case value
- Remove the labels for the same net (AVDD1-AVDD6)
- They are changed on text now
- Resistor values marked as 30E, 200E, 49E9 -> 49R9, 30
- Done
- Over-design of decoupling. Make it simpler, 10nF not needed. But
suggest to add an inductor. (Cf. ADC100M: just two 100nF and 4.7uH
inductor: 67.7 dB, 70.8 dB, 72.2 dB (@ /-50mV,/-0.5V, +/-5V range)
measured, while it has 4 channels and full front-end. AD9645 spec:
SNR = 74 dBFS (to Nyquist).)
- We will probably do two different cards with different decoupling scheme to be able to see the influence of decoupling
- Specify input range
- Done
- Specify transformer type and tell which winding ratio.
- Already in the detailed schematics PDF
- Why 30 Ohm and not 33 Ohm as specified in datasheet on VINA/B?
- These resistor have to be in Metal Film (less noisy). We have not found them in 33 ohm. That is why we use 30 ohm instead. The input impedance is a bit modified but still acceptable
- Why not use a 4-channel ADC so that there can be no skew problems?
- The biggest change for the new design
Sheet 5: ADC Clock splitter
-
As we have decided to use an other ADC with 4 input channels, we no longer need a clock splitter circuit. However, the LTC6957 is now used as a clock driver.
- Note of version IC: add below component.
- Done
- Max speed 300 MHz, specify on schematics
- Done
- Repeat table of input filter. Tell what are the default settings.
- Done
- J1 not specified what type of connector.
- These connectors are jumpers. The references are added
- As want to sample with 125 MHz, and max 300 MHz on splitter, may
possibly limit.
- The ADC only needs a clock signal of 125 MHz if we do not use the internal clock divider. As we have decided to use a high quality 125 MHz clock at the input, this feature is not used and we do not use a clock input greater than 125 MHz
- Why no local clock oscillator and require a stable external one? Add
one.
- Done
- Use a power splitter instead of a clock splitter IC
- The component is not used as clock splitter anymore
- Link the filter inputs to vcc using pull-ups to have a default
configuration
- I preferred to connect them to the ground to get the maximum cut off frequency
- Note of version IC: add below component.
Sheet 6: Connections to the MicroZED board
- What are all L1-L6 etc? Not specified.
- Already in the detailed schematics PDF. Will be put in the not detailed schematics PDF for the new design
- Why are the double labels for? Makes schematics look weird.
- These labels are there to be able to show the connections between the ADC and the MicroZed on the main hierarchical page but also to be able to connect these pins to the external connectors at the same time. This has been removed for the new design
- Maybe add some buffers between the ADC and the FPGA
- We will not add some buffer between the ADC and the FPGA. These buffer would isolate the ADC from the noisy MicroZed,bu this would complicate the design
Sheet 7: Connections to the MicroZED board 2
- 10nF not of much use as connectors to it. Better have 10uF as is
consuming a lot and may have large peaks
- Done
- Why comment PG_MODULE?
- this pin can be connected to a LED to tell the user the startup sequence is finished. This pin has been linked to a LED in the new schematics
- Banks that are not used for the ADC should be connected to the 3.3 V
instead of 1.8 V (more common)
- Done
- Add a reset switch on the pin CARRIER_SRST (see carrier card
datasheet)
- Not usefull, there is also a restart button on the MicroZed itself
- Add a note concerning the MicroZed compatibilities
- Done. The prototype will be realised with the MicroZed
Sheet 8: Connectors on the side of the board
- Remove some GPIO connections (40 pins are enough)
- Only the GPIO for the bank 35 are provided (powered with 3.3 V)
- Put the GPIO connectors to be compatible with designs done for the
MicroZed GPIO carrier
card
- These connectors using the same connectors as the IO carrier card ones. Unfortunately, we only provide the connectors for the bank 35. The bank 34 is used for the ADC is powered with 1.8 V
Bill of Materials
- Made by hand and not extracted from schematics. Prone to errors when
modifying.
- Done by hand but corrected using the BOM list export from Kicad
- Missing manufacturer name
- Will be taken into account for the next design
- Very expensive components used everywhere. Almost 100 Euro on C and
R alone.
- Will be taken into account for the next design
- Really 0.1% needed?
- Not everywhere, this remark will be taken into account for the next design
- 16 C values (for the ADC100M only 12 C values, and has a full
front-end) (R: 9 types, for the ADC100M : 18, so is good)
- Will be taken into account for the next design
- MicroZED should likely be put on BOM
- Will be taken into account for the next design
- Why two types of SMA?
- We need two types of SMA : for the connectors at the edges of the board : these connectors are horizontal, and for the connectors which are in the middle of the board (these are vertical)
- Prices, have fixed two digits (69, 4.6, 0.58)
- Will be taken into account for the next design
Comments on the layout
- Avoid small angles while crossing the tracks (better to cross with
90°)
- Will be taken into account for the next design
- Avoid to cross the power junction with the differential tracks
(local impedance mismatch)
- Will be taken into account for the next design
- Put the decoupling capacitors on the top of the board if possible.
- Will be taken into account for the next design
- Bigger distance between the SMA connectors to be able to screw the
male connector easier
- Will be taken into account for the next design
Other Comments on the written documentation: "Realisation of a low noise acquisition board : design choices"
- Missing name of author.
- Will be corrected as soon as possible
- Choices not made clear (The minimum specifications are 12 bits with
an LVDS output.)
- Will be taken into account for the next design
- Texas InstrumentS, some French words used, some typos (MicroZeb
Board)
- Will be corrected as soon as possible