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Getting Started with the SPEC
Commit fa76945d authored by garcialasheras's avatar garcialasheras
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First version of the Getting Started with the SPEC code

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[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
README
View file @ fa76945d
FEBRUARY 2014
DATE 20140224
THIS IS JUST A SANDBOX -- ACTUAL WORK IS UNDER DEVELOPMENT!!
THE REPOSITORY IS BEING CONTINUOUSLY CLEANED AND RE-INITIALIZED AS THE FIRST BETA VERSION IS NOT RELEASED YET
PLEASE, DON'T TRUST THIS CODE ;-)
JAVI
First version of the Getting Started with the SPEC project is released.
hdl/.gitignore 0 → 100644
View file @ fa76945d
*.*\#
\#*
.\#*
*.*~
work
*.wlf
modelsim.ini
transcript
*.vstf
*.bak
*.vcd
*.h
*.o
*.bin
*.elf
Makefile
general-cores @ fc55d71b
Subproject commit fc55d71bb81f86c2f4770b3fae8da0b15d096316
gn4124-core @ f26b97a5
Subproject commit f26b97a564b43c8119ef7dd8e156088ab9346390
hdl/modules/fmc_dio_ch5_ttl/Manifest.py 0 → 100644
View file @ fa76945d
files = ["fmc_dio_ch5_ttl.vhd", "wb_slave_fmc_dio_ch5_ttl.vhd" ]
hdl/modules/fmc_dio_ch5_ttl/build_wb.sh 0 → 100755
View file @ fa76945d
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/wb_slave_fmc_dio_ch5_ttl.in -f texinfo wb_slave_fmc_dio_ch5_ttl.wb
wbgen2 -D ./doc/wb_slave_fmc_dio_ch5_ttl.html -V wb_slave_fmc_dio_ch5_ttl.vhd -H signals --lang vhdl wb_slave_fmc_dio_ch5_ttl.wb
hdl/modules/fmc_dio_ch5_ttl/doc/wb_slave_fmc_dio_ch5_ttl.html 0 → 100644
View file @ fa76945d
<HTML>
<HEAD>
<TITLE>wb_slave_fmc_dio_5ch_ttl</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
BODY { background: white; color: black;
font-family: Arial,Helvetica; font-size:12; }
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.td_arrow_right { padding:0px; background: #ffffff; text-align: left; font-size:12;}
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.td_desc { padding: 3px; }
.td_sym_center { background: #e0e0f0; padding: 3px; }
.td_port_name { font-family:Courier New,Courier; background: #e0e0f0; text-align: right; font-weight:bold;padding: 3px; width:200px; }
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-->
</STYLE>
</HEAD>
<BODY>
<h1 class="heading">wb_slave_fmc_dio_5ch_ttl</h1>
<h3>FMC DIO 5ch TTL Port</h3>
<p>A Wishbone interface for the FMC DIO 5ch TTL</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Pin direction register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Pin state register</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Pin output register</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Pin termination register</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Set output pin register</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">Clear output pin register</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">LED signaling interface</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#DDR">Pin direction register</a>
</td>
<td class="td_code">
fmc_dio_ddr
</td>
<td class="td_code">
DDR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#PSR">Pin state register</a>
</td>
<td class="td_code">
fmc_dio_psr
</td>
<td class="td_code">
PSR
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#PDR">Pin output register</a>
</td>
<td class="td_code">
fmc_dio_pdr
</td>
<td class="td_code">
PDR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#TERM">Pin termination register</a>
</td>
<td class="td_code">
fmc_dio_term
</td>
<td class="td_code">
TERM
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x4
</td>
<td >
REG
</td>
<td >
<A href="#SOPR">Set output pin register</a>
</td>
<td class="td_code">
fmc_dio_sopr
</td>
<td class="td_code">
SOPR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x5
</td>
<td >
REG
</td>
<td >
<A href="#COPR">Clear output pin register</a>
</td>
<td class="td_code">
fmc_dio_copr
</td>
<td class="td_code">
COPR
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x8
</td>
<td >
REG
</td>
<td >
<A href="#LEDS">LED signaling interface</a>
</td>
<td class="td_code">
fmc_dio_leds
</td>
<td class="td_code">
LEDS
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Pin direction register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
clk_sys_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_dio_ddr_o[4:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_adr_i[3:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Pin state register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_dio_psr_i[4:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Pin output register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_dio_pdr_o[4:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_dio_pdr_wr_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Pin termination register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_dio_term_o[4:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Set output pin register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_dio_sopr_o[4:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_dio_sopr_wr_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Clear output pin register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_dio_copr_o[4:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_dio_copr_wr_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>LED signaling interface:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_dio_leds_bot_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_dio_leds_top_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="DDR"></a>
<h3><a name="sect_3_1">3.1. Pin direction register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_dio_ddr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
DDR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
A register defining the direction of the DIO pins.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=5 class="td_field">
DDR[4:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
DDR
</b>[<i>read/write</i>]: Pin directions
<br>Each bit in this register defines the direction of the corresponding pin in the DIO. 1 means the pin is an OUTPUT, 0 means the pin is an INPUT
</ul>
<a name="PSR"></a>
<h3><a name="sect_3_2">3.2. Pin state register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_dio_psr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
PSR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<p>
A register containing the current state of the DIO pins.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=5 class="td_field">
PSR[4:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
PSR
</b>[<i>read-only</i>]: Pin input state
<br>Each bit in this register reflects the state of the corresponding pin in the DIO. 1 means the pin is HIGH, 0 means the pin is LOW
</ul>
<a name="PDR"></a>
<h3><a name="sect_3_3">3.3. Pin output register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_dio_pdr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
PDR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<p>
A register that allows changing the value of the DIO pins by means of a direct write access
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=5 class="td_field">
PDR[4:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
PDR
</b>[<i>write-only</i>]: Pin output value
</ul>
<a name="TERM"></a>
<h3><a name="sect_3_4">3.4. Pin termination register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_dio_term
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TERM
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<p>
A register defining the use of the 50 Ohm termination
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=5 class="td_field">
TERM[4:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
TERM
</b>[<i>read/write</i>]: Pin terminations
<br>Writing '1' activates the termination resistor
</ul>
<a name="SOPR"></a>
<h3><a name="sect_3_5">3.5. Set output pin register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_dio_sopr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
SOPR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x10
</td>
</tr>
</table>
<p>
Writing '1' sets the corresponding DIO pin to '1'
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=5 class="td_field">
SOPR[4:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
SOPR
</b>[<i>write-only</i>]: Set output pin register
</ul>
<a name="COPR"></a>
<h3><a name="sect_3_6">3.6. Clear output pin register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_dio_copr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x5
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
COPR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x14
</td>
</tr>
</table>
<p>
Writing '1' clears the corresponding DIO pin
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=5 class="td_field">
COPR[4:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
COPR
</b>[<i>write-only</i>]: Clear output pin register
</ul>
<a name="LEDS"></a>
<h3><a name="sect_3_7">3.7. LED signaling interface</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc_dio_leds
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
LEDS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x20
</td>
</tr>
</table>
<p>
Writing '1' activates the corresponding LED
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
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-
</td>
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-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
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-
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-
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-
</td>
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-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
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<td class="td_unused">
-
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-
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-
</td>
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-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
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<td class="td_unused">
-
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-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TOP
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
BOT
</td>
</tr>
</table>
<ul>
<li><b>
BOT
</b>[<i>read/write</i>]: FMC DIO Bottom LED
<br>Control bit for the bottom LED placed on the FMC DIO front panel
<li><b>
TOP
</b>[<i>read/write</i>]: FMC DIO Top LED
<br>Control bit for the top LED placed on the FMC DIO front panel
</ul>
</BODY>
</HTML>
hdl/modules/fmc_dio_ch5_ttl/doc/wb_slave_fmc_dio_ch5_ttl.in 0 → 100644
View file @ fa76945d
@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{ddr} @tab
Pin direction register
@item @code{0x4} @tab
REG @tab
@code{psr} @tab
Pin state register
@item @code{0x8} @tab
REG @tab
@code{pdr} @tab
Pin output register
@item @code{0xc} @tab
REG @tab
@code{term} @tab
Pin termination register
@item @code{0x10} @tab
REG @tab
@code{sopr} @tab
Set output pin register
@item @code{0x14} @tab
REG @tab
@code{copr} @tab
Clear output pin register
@item @code{0x20} @tab
REG @tab
@code{leds} @tab
LED signaling interface
@end multitable
@regsection @code{ddr} - Pin direction register
A register defining the direction of the DIO pins.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab R/W @tab
@code{DDR}
@tab @code{0} @tab
Pin directions
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ddr} @tab Each bit in this register defines the direction of the corresponding pin in the DIO. 1 means the pin is an OUTPUT, 0 means the pin is an INPUT
@end multitable
@regsection @code{psr} - Pin state register
A register containing the current state of the DIO pins.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab R/O @tab
@code{PSR}
@tab @code{X} @tab
Pin input state
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{psr} @tab Each bit in this register reflects the state of the corresponding pin in the DIO. 1 means the pin is HIGH, 0 means the pin is LOW
@end multitable
@regsection @code{pdr} - Pin output register
A register that allows changing the value of the DIO pins by means of a direct write access
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab W/O @tab
@code{PDR}
@tab @code{0} @tab
Pin output value
@end multitable
@regsection @code{term} - Pin termination register
A register defining the use of the 50 Ohm termination
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab R/W @tab
@code{TERM}
@tab @code{0} @tab
Pin terminations
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{term} @tab Writing '1' activates the termination resistor
@end multitable
@regsection @code{sopr} - Set output pin register
Writing '1' sets the corresponding DIO pin to '1'
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab W/O @tab
@code{SOPR}
@tab @code{0} @tab
Set output pin register
@end multitable
@regsection @code{copr} - Clear output pin register
Writing '1' clears the corresponding DIO pin
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{4...0}
@tab W/O @tab
@code{COPR}
@tab @code{0} @tab
Clear output pin register
@end multitable
@regsection @code{leds} - LED signaling interface
Writing '1' activates the corresponding LED
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/W @tab
@code{BOT}
@tab @code{0} @tab
FMC DIO Bottom LED
@item @code{1}
@tab R/W @tab
@code{TOP}
@tab @code{0} @tab
FMC DIO Top LED
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{bot} @tab Control bit for the bottom LED placed on the FMC DIO front panel
@item @code{top} @tab Control bit for the top LED placed on the FMC DIO front panel
@end multitable
hdl/modules/fmc_dio_ch5_ttl/fmc_dio_ch5_ttl.vhd 0 → 100644
View file @ fa76945d
-------------------------------------------------------------------------------
-- Title : FMC DIO Ch5 TTL
-- Project : SPEC-getting-started
-------------------------------------------------------------------------------
-- File : fmc_dio_ch5_ttl.vhd
-- Author : Javier D. Garcia-Lasheras
-- Created : 2014-02-24
-- Last update: 2014-02-24
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Very simple core for handling the fmc-dio-ch5ttl module.
-- It allows a direct access to the FMC pins that control the basic functions.
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
-------------------------------------------------------------------------------
-- License : LGPLv3 or Later
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-02-24 1.0 jdgl Created
-------------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.wishbone_pkg.all;
entity fmc_dio_ch5_ttl is
port (
-- Whishbone Interface
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- FMC DIO 5ch TTL port
dio_clk_p_i : in std_logic;
dio_clk_n_i : in std_logic;
dio_n_i : in std_logic_vector(4 downto 0);
dio_p_i : in std_logic_vector(4 downto 0);
dio_n_o : out std_logic_vector(4 downto 0);
dio_p_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_term_en_o : out std_logic_vector(4 downto 0);
dio_led_bot_o : out std_logic;
dio_led_top_o : out std_logic
);
end fmc_dio_ch5_ttl;
architecture rtl of fmc_dio_ch5_ttl is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component wb_slave_fmc_dio_5ch_ttl is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fmc_dio_async_clk_i : in std_logic;
-- Port for std_logic_vector field: 'Pin directions' in reg: 'Pin direction register'
fmc_dio_ddr_o : out std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'Pin input state' in reg: 'Pin input state register'
fmc_dio_psr_i : in std_logic_vector(4 downto 0);
-- Ports for PASS_THROUGH field: 'Port output value' in reg: 'Port output register'
fmc_dio_pdr_o : out std_logic_vector(4 downto 0);
fmc_dio_pdr_wr_o : out std_logic;
-- Port for std_logic_vector field: 'Pin terminations' in reg: 'Pin termination register'
fmc_dio_term_o : out std_logic_vector(4 downto 0);
-- Ports for PASS_THROUGH field: 'Set output pin register' in reg: 'Set output pin register'
fmc_dio_sopr_o : out std_logic_vector(4 downto 0);
fmc_dio_sopr_wr_o : out std_logic;
-- Ports for PASS_THROUGH field: 'Clear output pin register' in reg: 'Clear output pin register'
fmc_dio_copr_o : out std_logic_vector(4 downto 0);
fmc_dio_copr_wr_o : out std_logic;
-- Port for BIT field: 'FMC DIO Bottom LED' in reg: 'LED signaling interface'
fmc_dio_leds_bot_o : out std_logic;
-- Port for BIT field: 'FMC DIO Top LED' in reg: 'LED signaling interface'
fmc_dio_leds_top_o : out std_logic
);
end component; -- wb_slave_fmc_dio_5ch_ttl
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal dio_in : std_logic_vector(4 downto 0);
signal dio_out : std_logic_vector(4 downto 0);
signal dio_clk : std_logic;
signal dio_bus_ddr_o : std_logic_vector(4 downto 0);
signal dio_bus_psr_i : std_logic_vector(4 downto 0);
signal dio_bus_pdr_o : std_logic_vector(4 downto 0);
signal dio_bus_pdr_wr_o : std_logic;
signal dio_bus_term_o : std_logic_vector(4 downto 0);
signal dio_bus_sopr_o : std_logic_vector(4 downto 0);
signal dio_bus_sopr_wr_o : std_logic;
signal dio_bus_copr_o : std_logic_vector(4 downto 0);
signal dio_bus_copr_wr_o : std_logic;
-- regsiter containing current output state
signal dio_reg : std_logic_vector(4 downto 0);
-- registers for synchronization of input pins
signal dio_pins_sync1 : std_logic_vector(4 downto 0);
signal dio_pins_sync0 : std_logic_vector(4 downto 0);
begin
gen_dio_iobufs : for i in 0 to 4 generate
-- Digital Input Differential Signaling Buffers
U_ibuf : IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => dio_in(i),
I => dio_p_i(i),
IB => dio_n_i(i)
);
-- Digital Output Differential Signaling Buffers
U_obuf : OBUFDS
port map (
I => dio_out(i),
O => dio_p_o(i),
OB => dio_n_o(i)
);
end generate gen_dio_iobufs;
-- Clock Input Differential Signaling Buffer
U_input_buffer : IBUFDS
generic map (
DIFF_TERM => true)
port map (
O => dio_clk,
I => dio_clk_p_i,
IB => dio_clk_n_i
);
wb_dio_port : wb_slave_fmc_dio_5ch_ttl
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_adr_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
fmc_dio_async_clk_i => clk_sys_i,
fmc_dio_ddr_o => dio_bus_ddr_o,
fmc_dio_psr_i => dio_bus_psr_i,
fmc_dio_pdr_o => dio_bus_pdr_o,
fmc_dio_pdr_wr_o => dio_bus_pdr_wr_o,
fmc_dio_term_o => dio_bus_term_o,
fmc_dio_sopr_o => dio_bus_sopr_o,
fmc_dio_sopr_wr_o => dio_bus_sopr_wr_o,
fmc_dio_copr_o => dio_bus_copr_o,
fmc_dio_copr_wr_o => dio_bus_copr_wr_o,
fmc_dio_leds_bot_o => dio_led_bot_o,
fmc_dio_leds_top_o => dio_led_top_o
);
-- FMC DIO REGISTERS HANDLING
process (clk_sys_i, rst_n_i)
begin -- process
if(rst_n_i = '0') then
dio_reg <= (others => '0');
elsif rising_edge(clk_sys_i) then
if(dio_bus_pdr_wr_o = '1') then -- write operation to "PDR" register
-- set the new values of GPIO outputs
dio_reg <= dio_bus_pdr_o;
end if;
if(dio_bus_sopr_wr_o = '1') then -- write to "SOPR" reg - set ones
for i in 0 to 4 loop
if(dio_bus_sopr_o(i) = '1') then
dio_reg(i) <= '1';
end if;
end loop;
end if;
if(dio_bus_copr_wr_o = '1') then -- write to "COPR" reg - set zeros
for i in 0 to 4 loop
if(dio_bus_copr_o(i) = '1') then
dio_reg(i) <= '0';
end if;
end loop;
end if;
end if;
end process;
-- synchronizing process for input pins
synchronize_input_pins : process (clk_sys_i, rst_n_i)
begin -- process
if(rst_n_i = '0') then
dio_pins_sync0 <= (others => '0');
dio_pins_sync1 <= (others => '0');
elsif rising_edge(clk_sys_i) then
dio_pins_sync0 <= dio_in;
dio_pins_sync1 <= dio_pins_sync0;
end if;
end process;
-- generate the pin interface for I/O channels
gen_pin_interface : for i in 0 to 4 generate
dio_bus_psr_i(i) <= dio_pins_sync1(i) when dio_bus_ddr_o(i) = '0' else dio_reg(i);
dio_out(i) <= dio_reg(i);
dio_oe_n_o(i) <= not dio_bus_ddr_o(i);
dio_term_en_o(i) <= dio_bus_term_o(i);
end generate gen_pin_interface;
end rtl;
hdl/modules/fmc_dio_ch5_ttl/wb_slave_fmc_dio_ch5_ttl.vhd 0 → 100644
View file @ fa76945d
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC DIO 5ch TTL Port
---------------------------------------------------------------------------------------
-- File : wb_slave_fmc_dio_ch5_ttl.vhd
-- Author : auto-generated by wbgen2 from wb_slave_fmc_dio_ch5_ttl.wb
-- Created : Mon Feb 24 02:35:48 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_slave_fmc_dio_ch5_ttl.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wb_slave_fmc_dio_5ch_ttl is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fmc_dio_async_clk_i : in std_logic;
-- Port for asynchronous (clock: fmc_dio_async_clk_i) std_logic_vector field: 'Pin directions' in reg: 'Pin direction register'
fmc_dio_ddr_o : out std_logic_vector(4 downto 0);
-- Port for asynchronous (clock: fmc_dio_async_clk_i) std_logic_vector field: 'Pin input state' in reg: 'Pin state register'
fmc_dio_psr_i : in std_logic_vector(4 downto 0);
-- Ports for asynchronous (clock: fmc_dio_async_clk_i) PASS_THROUGH field: 'Pin output value' in reg: 'Pin output register'
fmc_dio_pdr_o : out std_logic_vector(4 downto 0);
fmc_dio_pdr_wr_o : out std_logic;
-- Port for asynchronous (clock: fmc_dio_async_clk_i) std_logic_vector field: 'Pin terminations' in reg: 'Pin termination register'
fmc_dio_term_o : out std_logic_vector(4 downto 0);
-- Ports for asynchronous (clock: fmc_dio_async_clk_i) PASS_THROUGH field: 'Set output pin register' in reg: 'Set output pin register'
fmc_dio_sopr_o : out std_logic_vector(4 downto 0);
fmc_dio_sopr_wr_o : out std_logic;
-- Ports for asynchronous (clock: fmc_dio_async_clk_i) PASS_THROUGH field: 'Clear output pin register' in reg: 'Clear output pin register'
fmc_dio_copr_o : out std_logic_vector(4 downto 0);
fmc_dio_copr_wr_o : out std_logic;
-- Port for asynchronous (clock: fmc_dio_async_clk_i) BIT field: 'FMC DIO Bottom LED' in reg: 'LED signaling interface'
fmc_dio_leds_bot_o : out std_logic;
-- Port for asynchronous (clock: fmc_dio_async_clk_i) BIT field: 'FMC DIO Top LED' in reg: 'LED signaling interface'
fmc_dio_leds_top_o : out std_logic
);
end wb_slave_fmc_dio_5ch_ttl;
architecture syn of wb_slave_fmc_dio_5ch_ttl is
signal fmc_dio_ddr_int : std_logic_vector(4 downto 0);
signal fmc_dio_ddr_swb : std_logic ;
signal fmc_dio_ddr_swb_delay : std_logic ;
signal fmc_dio_ddr_swb_s0 : std_logic ;
signal fmc_dio_ddr_swb_s1 : std_logic ;
signal fmc_dio_ddr_swb_s2 : std_logic ;
signal fmc_dio_psr_int : std_logic_vector(4 downto 0);
signal fmc_dio_psr_lwb : std_logic ;
signal fmc_dio_psr_lwb_delay : std_logic ;
signal fmc_dio_psr_lwb_in_progress : std_logic ;
signal fmc_dio_psr_lwb_s0 : std_logic ;
signal fmc_dio_psr_lwb_s1 : std_logic ;
signal fmc_dio_psr_lwb_s2 : std_logic ;
signal fmc_dio_pdr_wr_int : std_logic ;
signal fmc_dio_pdr_wr_int_delay : std_logic ;
signal fmc_dio_pdr_wr_sync0 : std_logic ;
signal fmc_dio_pdr_wr_sync1 : std_logic ;
signal fmc_dio_pdr_wr_sync2 : std_logic ;
signal fmc_dio_term_int : std_logic_vector(4 downto 0);
signal fmc_dio_term_swb : std_logic ;
signal fmc_dio_term_swb_delay : std_logic ;
signal fmc_dio_term_swb_s0 : std_logic ;
signal fmc_dio_term_swb_s1 : std_logic ;
signal fmc_dio_term_swb_s2 : std_logic ;
signal fmc_dio_sopr_wr_int : std_logic ;
signal fmc_dio_sopr_wr_int_delay : std_logic ;
signal fmc_dio_sopr_wr_sync0 : std_logic ;
signal fmc_dio_sopr_wr_sync1 : std_logic ;
signal fmc_dio_sopr_wr_sync2 : std_logic ;
signal fmc_dio_copr_wr_int : std_logic ;
signal fmc_dio_copr_wr_int_delay : std_logic ;
signal fmc_dio_copr_wr_sync0 : std_logic ;
signal fmc_dio_copr_wr_sync1 : std_logic ;
signal fmc_dio_copr_wr_sync2 : std_logic ;
signal fmc_dio_leds_bot_int : std_logic ;
signal fmc_dio_leds_bot_sync0 : std_logic ;
signal fmc_dio_leds_bot_sync1 : std_logic ;
signal fmc_dio_leds_top_int : std_logic ;
signal fmc_dio_leds_top_sync0 : std_logic ;
signal fmc_dio_leds_top_sync1 : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(3 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
fmc_dio_ddr_int <= "00000";
fmc_dio_ddr_swb <= '0';
fmc_dio_ddr_swb_delay <= '0';
fmc_dio_psr_lwb <= '0';
fmc_dio_psr_lwb_delay <= '0';
fmc_dio_psr_lwb_in_progress <= '0';
fmc_dio_pdr_wr_int <= '0';
fmc_dio_pdr_wr_int_delay <= '0';
fmc_dio_term_int <= "00000";
fmc_dio_term_swb <= '0';
fmc_dio_term_swb_delay <= '0';
fmc_dio_sopr_wr_int <= '0';
fmc_dio_sopr_wr_int_delay <= '0';
fmc_dio_copr_wr_int <= '0';
fmc_dio_copr_wr_int_delay <= '0';
fmc_dio_leds_bot_int <= '0';
fmc_dio_leds_top_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
fmc_dio_ddr_swb <= fmc_dio_ddr_swb_delay;
fmc_dio_ddr_swb_delay <= '0';
fmc_dio_psr_lwb <= fmc_dio_psr_lwb_delay;
fmc_dio_psr_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_dio_psr_lwb_in_progress = '1')) then
rddata_reg(4 downto 0) <= fmc_dio_psr_int;
fmc_dio_psr_lwb_in_progress <= '0';
end if;
fmc_dio_pdr_wr_int <= fmc_dio_pdr_wr_int_delay;
fmc_dio_pdr_wr_int_delay <= '0';
fmc_dio_term_swb <= fmc_dio_term_swb_delay;
fmc_dio_term_swb_delay <= '0';
fmc_dio_sopr_wr_int <= fmc_dio_sopr_wr_int_delay;
fmc_dio_sopr_wr_int_delay <= '0';
fmc_dio_copr_wr_int <= fmc_dio_copr_wr_int_delay;
fmc_dio_copr_wr_int_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(3 downto 0) is
when "0000" =>
if (wb_we_i = '1') then
fmc_dio_ddr_int <= wrdata_reg(4 downto 0);
fmc_dio_ddr_swb <= '1';
fmc_dio_ddr_swb_delay <= '1';
end if;
rddata_reg(4 downto 0) <= fmc_dio_ddr_int;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0001" =>
if (wb_we_i = '1') then
end if;
if (wb_we_i = '0') then
fmc_dio_psr_lwb <= '1';
fmc_dio_psr_lwb_delay <= '1';
fmc_dio_psr_lwb_in_progress <= '1';
end if;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "0010" =>
if (wb_we_i = '1') then
fmc_dio_pdr_wr_int <= '1';
fmc_dio_pdr_wr_int_delay <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0011" =>
if (wb_we_i = '1') then
fmc_dio_term_int <= wrdata_reg(4 downto 0);
fmc_dio_term_swb <= '1';
fmc_dio_term_swb_delay <= '1';
end if;
rddata_reg(4 downto 0) <= fmc_dio_term_int;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0100" =>
if (wb_we_i = '1') then
fmc_dio_sopr_wr_int <= '1';
fmc_dio_sopr_wr_int_delay <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "0101" =>
if (wb_we_i = '1') then
fmc_dio_copr_wr_int <= '1';
fmc_dio_copr_wr_int_delay <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "1000" =>
if (wb_we_i = '1') then
fmc_dio_leds_bot_int <= wrdata_reg(0);
fmc_dio_leds_top_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= fmc_dio_leds_bot_int;
rddata_reg(1) <= fmc_dio_leds_top_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Pin directions
-- asynchronous std_logic_vector register : Pin directions (type RW/RO, fmc_dio_async_clk_i <-> clk_sys_i)
process (fmc_dio_async_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_dio_ddr_swb_s0 <= '0';
fmc_dio_ddr_swb_s1 <= '0';
fmc_dio_ddr_swb_s2 <= '0';
fmc_dio_ddr_o <= "00000";
elsif rising_edge(fmc_dio_async_clk_i) then
fmc_dio_ddr_swb_s0 <= fmc_dio_ddr_swb;
fmc_dio_ddr_swb_s1 <= fmc_dio_ddr_swb_s0;
fmc_dio_ddr_swb_s2 <= fmc_dio_ddr_swb_s1;
if ((fmc_dio_ddr_swb_s2 = '0') and (fmc_dio_ddr_swb_s1 = '1')) then
fmc_dio_ddr_o <= fmc_dio_ddr_int;
end if;
end if;
end process;
-- Pin input state
-- asynchronous std_logic_vector register : Pin input state (type RO/WO, fmc_dio_async_clk_i <-> clk_sys_i)
process (fmc_dio_async_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_dio_psr_lwb_s0 <= '0';
fmc_dio_psr_lwb_s1 <= '0';
fmc_dio_psr_lwb_s2 <= '0';
fmc_dio_psr_int <= "00000";
elsif rising_edge(fmc_dio_async_clk_i) then
fmc_dio_psr_lwb_s0 <= fmc_dio_psr_lwb;
fmc_dio_psr_lwb_s1 <= fmc_dio_psr_lwb_s0;
fmc_dio_psr_lwb_s2 <= fmc_dio_psr_lwb_s1;
if ((fmc_dio_psr_lwb_s1 = '1') and (fmc_dio_psr_lwb_s2 = '0')) then
fmc_dio_psr_int <= fmc_dio_psr_i;
end if;
end if;
end process;
-- Pin output value
-- pass-through field: Pin output value in register: Pin output register
fmc_dio_pdr_o <= wrdata_reg(4 downto 0);
process (fmc_dio_async_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_dio_pdr_wr_sync0 <= '0';
fmc_dio_pdr_wr_sync1 <= '0';
fmc_dio_pdr_wr_sync2 <= '0';
elsif rising_edge(fmc_dio_async_clk_i) then
fmc_dio_pdr_wr_sync0 <= fmc_dio_pdr_wr_int;
fmc_dio_pdr_wr_sync1 <= fmc_dio_pdr_wr_sync0;
fmc_dio_pdr_wr_sync2 <= fmc_dio_pdr_wr_sync1;
fmc_dio_pdr_wr_o <= fmc_dio_pdr_wr_sync1 and (not fmc_dio_pdr_wr_sync2);
end if;
end process;
-- Pin terminations
-- asynchronous std_logic_vector register : Pin terminations (type RW/RO, fmc_dio_async_clk_i <-> clk_sys_i)
process (fmc_dio_async_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_dio_term_swb_s0 <= '0';
fmc_dio_term_swb_s1 <= '0';
fmc_dio_term_swb_s2 <= '0';
fmc_dio_term_o <= "00000";
elsif rising_edge(fmc_dio_async_clk_i) then
fmc_dio_term_swb_s0 <= fmc_dio_term_swb;
fmc_dio_term_swb_s1 <= fmc_dio_term_swb_s0;
fmc_dio_term_swb_s2 <= fmc_dio_term_swb_s1;
if ((fmc_dio_term_swb_s2 = '0') and (fmc_dio_term_swb_s1 = '1')) then
fmc_dio_term_o <= fmc_dio_term_int;
end if;
end if;
end process;
-- Set output pin register
-- pass-through field: Set output pin register in register: Set output pin register
fmc_dio_sopr_o <= wrdata_reg(4 downto 0);
process (fmc_dio_async_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_dio_sopr_wr_sync0 <= '0';
fmc_dio_sopr_wr_sync1 <= '0';
fmc_dio_sopr_wr_sync2 <= '0';
elsif rising_edge(fmc_dio_async_clk_i) then
fmc_dio_sopr_wr_sync0 <= fmc_dio_sopr_wr_int;
fmc_dio_sopr_wr_sync1 <= fmc_dio_sopr_wr_sync0;
fmc_dio_sopr_wr_sync2 <= fmc_dio_sopr_wr_sync1;
fmc_dio_sopr_wr_o <= fmc_dio_sopr_wr_sync1 and (not fmc_dio_sopr_wr_sync2);
end if;
end process;
-- Clear output pin register
-- pass-through field: Clear output pin register in register: Clear output pin register
fmc_dio_copr_o <= wrdata_reg(4 downto 0);
process (fmc_dio_async_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_dio_copr_wr_sync0 <= '0';
fmc_dio_copr_wr_sync1 <= '0';
fmc_dio_copr_wr_sync2 <= '0';
elsif rising_edge(fmc_dio_async_clk_i) then
fmc_dio_copr_wr_sync0 <= fmc_dio_copr_wr_int;
fmc_dio_copr_wr_sync1 <= fmc_dio_copr_wr_sync0;
fmc_dio_copr_wr_sync2 <= fmc_dio_copr_wr_sync1;
fmc_dio_copr_wr_o <= fmc_dio_copr_wr_sync1 and (not fmc_dio_copr_wr_sync2);
end if;
end process;
-- FMC DIO Bottom LED
-- synchronizer chain for field : FMC DIO Bottom LED (type RW/RO, clk_sys_i <-> fmc_dio_async_clk_i)
process (fmc_dio_async_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_dio_leds_bot_o <= '0';
fmc_dio_leds_bot_sync0 <= '0';
fmc_dio_leds_bot_sync1 <= '0';
elsif rising_edge(fmc_dio_async_clk_i) then
fmc_dio_leds_bot_sync0 <= fmc_dio_leds_bot_int;
fmc_dio_leds_bot_sync1 <= fmc_dio_leds_bot_sync0;
fmc_dio_leds_bot_o <= fmc_dio_leds_bot_sync1;
end if;
end process;
-- FMC DIO Top LED
-- synchronizer chain for field : FMC DIO Top LED (type RW/RO, clk_sys_i <-> fmc_dio_async_clk_i)
process (fmc_dio_async_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_dio_leds_top_o <= '0';
fmc_dio_leds_top_sync0 <= '0';
fmc_dio_leds_top_sync1 <= '0';
elsif rising_edge(fmc_dio_async_clk_i) then
fmc_dio_leds_top_sync0 <= fmc_dio_leds_top_int;
fmc_dio_leds_top_sync1 <= fmc_dio_leds_top_sync0;
fmc_dio_leds_top_o <= fmc_dio_leds_top_sync1;
end if;
end process;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/modules/fmc_dio_ch5_ttl/wb_slave_fmc_dio_ch5_ttl.wb 0 → 100644
View file @ fa76945d
-- -*- Mode: LUA; tab-width: 4 -*-
-------------------------------------------------------------------------------
-- Title : WB Slave FMC DIO TTL
-- Project : SPEC-getting-started
-------------------------------------------------------------------------------
-- File : wb_slave_fmc_dio_ch5_ttl.wb
-- Author : Javier D. Garcia-Lasheras
-- Created : 2014-02-24
-- Last update: 2014-02-24
-- Standard : wb (Wishbone Generator)
-------------------------------------------------------------------------------
-- Description:
-- Wishbone generator file used in the SPEC getting started project.
-- It contains a slave description for controlling the basic functions
-- of the fmc-dio-ch5ttl module.
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
-------------------------------------------------------------------------------
-- License : LGPLv3 or Later
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-02-24 1.0 jdgl Created
-------------------------------------------------------------------------------
peripheral {
name = "FMC DIO 5ch TTL Port";
description = "A Wishbone interface for the FMC DIO 5ch TTL";
hdl_entity = "wb_slave_fmc_dio_5ch_ttl";
prefix = "fmc_dio";
reg {
name = "Pin direction register";
description = "A register defining the direction of the DIO pins.";
prefix = "ddr";
field {
name = "Pin directions";
description = "Each bit in this register defines the direction of the corresponding pin in the DIO. 1 means the pin is an OUTPUT, 0 means the pin is an INPUT";
type = SLV;
size = 5;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fmc_dio_async_clk_i";
};
};
reg {
name = "Pin state register";
description = "A register containing the current state of the DIO pins.";
prefix = "psr";
field {
name = "Pin input state";
description = "Each bit in this register reflects the state of the corresponding pin in the DIO. 1 means the pin is HIGH, 0 means the pin is LOW";
type = SLV;
size = 5;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "fmc_dio_async_clk_i";
};
};
reg {
name = "Pin output register";
description = "A register that allows changing the value of the DIO pins by means of a direct write access";
prefix = "pdr";
field {
name = "Pin output value";
type = PASS_THROUGH;
size = 5;
clock = "fmc_dio_async_clk_i";
};
};
reg {
name = "Pin termination register";
description = "A register defining the use of the 50 Ohm termination";
prefix = "term";
field {
name = "Pin terminations";
description = "Writing '1' activates the termination resistor";
type = SLV;
size = 5;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fmc_dio_async_clk_i";
};
};
reg {
name = "Set output pin register";
description = "Writing '1' sets the corresponding DIO pin to '1'";
prefix = "sopr";
align = 4;
field {
name = "Set output pin register";
type = PASS_THROUGH;
size = 5;
clock = "fmc_dio_async_clk_i";
};
};
reg {
name = "Clear output pin register";
description = "Writing '1' clears the corresponding DIO pin";
prefix = "copr";
field {
name = "Clear output pin register";
type = PASS_THROUGH;
size = 5;
clock = "fmc_dio_async_clk_i";
};
};
reg {
name = "LED signaling interface";
description = "Writing '1' activates the corresponding LED";
prefix = "leds";
align = 4;
field {
name = "FMC DIO Bottom LED";
description = "Control bit for the bottom LED placed on the FMC DIO front panel";
prefix = "bot";
type = BIT;
size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fmc_dio_async_clk_i";
};
field {
name = "FMC DIO Top LED";
description = "Control bit for the top LED placed on the FMC DIO front panel";
prefix = "top";
type = BIT;
size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "fmc_dio_async_clk_i";
};
};
};
hdl/modules/reset_generator/Manifest.py 0 → 100644
View file @ fa76945d
files = ["reset_generator.vhd"]
hdl/modules/reset_generator/reset_generator.vhd 0 → 100644
View file @ fa76945d
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity reset_generator is
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end reset_generator;
architecture behavioral of reset_generator is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal button_synced_n : std_logic;
signal pcie_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_pcie_n_a_i,
ppulse_o => pcie_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_button_n_a_i,
synced_o => button_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and button_synced_n and (not pcie_synced_n);
end behavioral;
hdl/modules/spec_user_interface/Manifest.py 0 → 100644
View file @ fa76945d
files = ["spec_user_interface.vhd"]
hdl/modules/spec_user_interface/build_wb.sh 0 → 100755
View file @ fa76945d
#!/bin/bash
mkdir -p doc
wbgen2 -D ./doc/spec_user_interface.in -f texinfo spec_user_interface.wb
wbgen2 -D ./doc/spec_user_interface.html -V spec_user_interface.vhd -H signals --lang vhdl spec_user_interface.wb
hdl/modules/spec_user_interface/doc/spec_user_interface.html 0 → 100644
View file @ fa76945d
<HTML>
<HEAD>
<TITLE>wb_slave_spec_user</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
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font-family: Arial,Helvetica; font-size:12; }
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h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
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.td_desc { padding: 3px; }
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.td_field { background: #e0e0f0; padding: 3px; text-align:center; }
.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
</STYLE>
</HEAD>
<BODY>
<h1 class="heading">wb_slave_spec_user</h1>
<h3>SPEC User Interface</h3>
<p>A sample 32-bit general-purpose SPEC user interface port</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Control register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Auxiliar interface</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#CTRL">Control register</a>
</td>
<td class="td_code">
spec_user_ctrl
</td>
<td class="td_code">
CTRL
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#AUX">Auxiliar interface</a>
</td>
<td class="td_code">
spec_user_aux
</td>
<td class="td_code">
AUX
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Control register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
clk_sys_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
spec_user_ctrl_ver_i[3:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_adr_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
spec_user_ctrl_led_green_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
spec_user_ctrl_led_red_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Auxiliar interface:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
spec_user_aux_button1_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
spec_user_aux_button2_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
spec_user_aux_leds_o[3:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="CTRL"></a>
<h3><a name="sect_3_1">3.1. Control register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
spec_user_ctrl
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CTRL
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
A register containing basic SPEC controls
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
LED_RED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
LED_GREEN
</td>
<td style="border: solid 1px black;" colspan=4 class="td_field">
VER[3:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
VER
</b>[<i>read-only</i>]: PCB Version
<br>This field accesses to the hard-wired 4 bits that indicate the PCB version
<li><b>
LED_GREEN
</b>[<i>read/write</i>]: Front panel green LED
<br>Control bit for the green LED placed on the SPEC front panel
<li><b>
LED_RED
</b>[<i>read/write</i>]: Front panel red LED
<br>Control bit for the red LED placed on the SPEC front panel
</ul>
<a name="AUX"></a>
<h3><a name="sect_3_2">3.2. Auxiliar interface</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
spec_user_aux
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
AUX
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<p>
A register mapping the SPEC internal auxiliar interface
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=4 class="td_field">
LEDS[3:0]
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
BUTTON2
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
BUTTON1
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
BUTTON1
</b>[<i>read-only</i>]: User Push-button 1
<br>Status bit for the internal push-button 1
<li><b>
BUTTON2
</b>[<i>read-only</i>]: User Push-button 2
<br>Status bit for the internal push-button 2
<li><b>
LEDS
</b>[<i>read/write</i>]: User Leds
<br>Control field for the 4 internal auxiliar LEDs
</ul>
</BODY>
</HTML>
hdl/modules/spec_user_interface/doc/spec_user_interface.in 0 → 100644
View file @ fa76945d
@regsection Memory map summary
@multitable @columnfractions .10 .15 .15 .55
@headitem Address @tab Type @tab Prefix @tab Name
@item @code{0x0} @tab
REG @tab
@code{ctrl} @tab
Control register
@item @code{0x4} @tab
REG @tab
@code{aux} @tab
Auxiliar interface
@end multitable
@regsection @code{ctrl} - Control register
A register containing basic SPEC controls
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{3...0}
@tab R/O @tab
@code{VER}
@tab @code{X} @tab
PCB Version
@item @code{4}
@tab R/W @tab
@code{LED_GREEN}
@tab @code{0} @tab
Front panel green LED
@item @code{5}
@tab R/W @tab
@code{LED_RED}
@tab @code{0} @tab
Front panel red LED
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ver} @tab This field accesses to the hard-wired 4 bits that indicate the PCB version
@item @code{led_green} @tab Control bit for the green LED placed on the SPEC front panel
@item @code{led_red} @tab Control bit for the red LED placed on the SPEC front panel
@end multitable
@regsection @code{aux} - Auxiliar interface
A register mapping the SPEC internal auxiliar interface
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{0}
@tab R/O @tab
@code{BUTTON1}
@tab @code{X} @tab
User Push-button 1
@item @code{1}
@tab R/O @tab
@code{BUTTON2}
@tab @code{X} @tab
User Push-button 2
@item @code{5...2}
@tab R/W @tab
@code{LEDS}
@tab @code{0} @tab
User Leds
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{button1} @tab Status bit for the internal push-button 1
@item @code{button2} @tab Status bit for the internal push-button 2
@item @code{leds} @tab Control field for the 4 internal auxiliar LEDs
@end multitable
hdl/modules/spec_user_interface/spec_user_interface.vhd 0 → 100644
View file @ fa76945d
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for SPEC User Interface
---------------------------------------------------------------------------------------
-- File : spec_user_interface.vhd
-- Author : auto-generated by wbgen2 from spec_user_interface.wb
-- Created : Mon Feb 24 01:47:14 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE spec_user_interface.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wb_slave_spec_user is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
spec_user_clk_i : in std_logic;
-- Port for asynchronous (clock: spec_user_clk_i) std_logic_vector field: 'PCB Version' in reg: 'Control register'
spec_user_ctrl_ver_i : in std_logic_vector(3 downto 0);
-- Port for asynchronous (clock: spec_user_clk_i) BIT field: 'Front panel green LED' in reg: 'Control register'
spec_user_ctrl_led_green_o : out std_logic;
-- Port for asynchronous (clock: spec_user_clk_i) BIT field: 'Front panel red LED' in reg: 'Control register'
spec_user_ctrl_led_red_o : out std_logic;
-- Port for asynchronous (clock: spec_user_clk_i) BIT field: 'User Push-button 1' in reg: 'Auxiliar interface'
spec_user_aux_button1_i : in std_logic;
-- Port for asynchronous (clock: spec_user_clk_i) BIT field: 'User Push-button 2' in reg: 'Auxiliar interface'
spec_user_aux_button2_i : in std_logic;
-- Port for asynchronous (clock: spec_user_clk_i) std_logic_vector field: 'User Leds' in reg: 'Auxiliar interface'
spec_user_aux_leds_o : out std_logic_vector(3 downto 0)
);
end wb_slave_spec_user;
architecture syn of wb_slave_spec_user is
signal spec_user_ctrl_ver_int : std_logic_vector(3 downto 0);
signal spec_user_ctrl_ver_lwb : std_logic ;
signal spec_user_ctrl_ver_lwb_delay : std_logic ;
signal spec_user_ctrl_ver_lwb_in_progress : std_logic ;
signal spec_user_ctrl_ver_lwb_s0 : std_logic ;
signal spec_user_ctrl_ver_lwb_s1 : std_logic ;
signal spec_user_ctrl_ver_lwb_s2 : std_logic ;
signal spec_user_ctrl_led_green_int : std_logic ;
signal spec_user_ctrl_led_green_sync0 : std_logic ;
signal spec_user_ctrl_led_green_sync1 : std_logic ;
signal spec_user_ctrl_led_red_int : std_logic ;
signal spec_user_ctrl_led_red_sync0 : std_logic ;
signal spec_user_ctrl_led_red_sync1 : std_logic ;
signal spec_user_aux_button1_sync0 : std_logic ;
signal spec_user_aux_button1_sync1 : std_logic ;
signal spec_user_aux_button2_sync0 : std_logic ;
signal spec_user_aux_button2_sync1 : std_logic ;
signal spec_user_aux_leds_int : std_logic_vector(3 downto 0);
signal spec_user_aux_leds_swb : std_logic ;
signal spec_user_aux_leds_swb_delay : std_logic ;
signal spec_user_aux_leds_swb_s0 : std_logic ;
signal spec_user_aux_leds_swb_s1 : std_logic ;
signal spec_user_aux_leds_swb_s2 : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(0 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
spec_user_ctrl_ver_lwb <= '0';
spec_user_ctrl_ver_lwb_delay <= '0';
spec_user_ctrl_ver_lwb_in_progress <= '0';
spec_user_ctrl_led_green_int <= '0';
spec_user_ctrl_led_red_int <= '0';
spec_user_aux_leds_int <= "0000";
spec_user_aux_leds_swb <= '0';
spec_user_aux_leds_swb_delay <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
spec_user_ctrl_ver_lwb <= spec_user_ctrl_ver_lwb_delay;
spec_user_ctrl_ver_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (spec_user_ctrl_ver_lwb_in_progress = '1')) then
rddata_reg(3 downto 0) <= spec_user_ctrl_ver_int;
spec_user_ctrl_ver_lwb_in_progress <= '0';
end if;
spec_user_aux_leds_swb <= spec_user_aux_leds_swb_delay;
spec_user_aux_leds_swb_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(0) is
when '0' =>
if (wb_we_i = '1') then
spec_user_ctrl_led_green_int <= wrdata_reg(4);
spec_user_ctrl_led_red_int <= wrdata_reg(5);
end if;
if (wb_we_i = '0') then
spec_user_ctrl_ver_lwb <= '1';
spec_user_ctrl_ver_lwb_delay <= '1';
spec_user_ctrl_ver_lwb_in_progress <= '1';
end if;
rddata_reg(4) <= spec_user_ctrl_led_green_int;
rddata_reg(5) <= spec_user_ctrl_led_red_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when '1' =>
if (wb_we_i = '1') then
spec_user_aux_leds_int <= wrdata_reg(5 downto 2);
spec_user_aux_leds_swb <= '1';
spec_user_aux_leds_swb_delay <= '1';
end if;
rddata_reg(0) <= spec_user_aux_button1_sync1;
rddata_reg(1) <= spec_user_aux_button2_sync1;
rddata_reg(5 downto 2) <= spec_user_aux_leds_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- PCB Version
-- asynchronous std_logic_vector register : PCB Version (type RO/WO, spec_user_clk_i <-> clk_sys_i)
process (spec_user_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
spec_user_ctrl_ver_lwb_s0 <= '0';
spec_user_ctrl_ver_lwb_s1 <= '0';
spec_user_ctrl_ver_lwb_s2 <= '0';
spec_user_ctrl_ver_int <= "0000";
elsif rising_edge(spec_user_clk_i) then
spec_user_ctrl_ver_lwb_s0 <= spec_user_ctrl_ver_lwb;
spec_user_ctrl_ver_lwb_s1 <= spec_user_ctrl_ver_lwb_s0;
spec_user_ctrl_ver_lwb_s2 <= spec_user_ctrl_ver_lwb_s1;
if ((spec_user_ctrl_ver_lwb_s1 = '1') and (spec_user_ctrl_ver_lwb_s2 = '0')) then
spec_user_ctrl_ver_int <= spec_user_ctrl_ver_i;
end if;
end if;
end process;
-- Front panel green LED
-- synchronizer chain for field : Front panel green LED (type RW/RO, clk_sys_i <-> spec_user_clk_i)
process (spec_user_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
spec_user_ctrl_led_green_o <= '0';
spec_user_ctrl_led_green_sync0 <= '0';
spec_user_ctrl_led_green_sync1 <= '0';
elsif rising_edge(spec_user_clk_i) then
spec_user_ctrl_led_green_sync0 <= spec_user_ctrl_led_green_int;
spec_user_ctrl_led_green_sync1 <= spec_user_ctrl_led_green_sync0;
spec_user_ctrl_led_green_o <= spec_user_ctrl_led_green_sync1;
end if;
end process;
-- Front panel red LED
-- synchronizer chain for field : Front panel red LED (type RW/RO, clk_sys_i <-> spec_user_clk_i)
process (spec_user_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
spec_user_ctrl_led_red_o <= '0';
spec_user_ctrl_led_red_sync0 <= '0';
spec_user_ctrl_led_red_sync1 <= '0';
elsif rising_edge(spec_user_clk_i) then
spec_user_ctrl_led_red_sync0 <= spec_user_ctrl_led_red_int;
spec_user_ctrl_led_red_sync1 <= spec_user_ctrl_led_red_sync0;
spec_user_ctrl_led_red_o <= spec_user_ctrl_led_red_sync1;
end if;
end process;
-- User Push-button 1
-- synchronizer chain for field : User Push-button 1 (type RO/WO, spec_user_clk_i -> clk_sys_i)
process (spec_user_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
spec_user_aux_button1_sync0 <= '0';
spec_user_aux_button1_sync1 <= '0';
elsif rising_edge(spec_user_clk_i) then
spec_user_aux_button1_sync0 <= spec_user_aux_button1_i;
spec_user_aux_button1_sync1 <= spec_user_aux_button1_sync0;
end if;
end process;
-- User Push-button 2
-- synchronizer chain for field : User Push-button 2 (type RO/WO, spec_user_clk_i -> clk_sys_i)
process (spec_user_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
spec_user_aux_button2_sync0 <= '0';
spec_user_aux_button2_sync1 <= '0';
elsif rising_edge(spec_user_clk_i) then
spec_user_aux_button2_sync0 <= spec_user_aux_button2_i;
spec_user_aux_button2_sync1 <= spec_user_aux_button2_sync0;
end if;
end process;
-- User Leds
-- asynchronous std_logic_vector register : User Leds (type RW/RO, spec_user_clk_i <-> clk_sys_i)
process (spec_user_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
spec_user_aux_leds_swb_s0 <= '0';
spec_user_aux_leds_swb_s1 <= '0';
spec_user_aux_leds_swb_s2 <= '0';
spec_user_aux_leds_o <= "0000";
elsif rising_edge(spec_user_clk_i) then
spec_user_aux_leds_swb_s0 <= spec_user_aux_leds_swb;
spec_user_aux_leds_swb_s1 <= spec_user_aux_leds_swb_s0;
spec_user_aux_leds_swb_s2 <= spec_user_aux_leds_swb_s1;
if ((spec_user_aux_leds_swb_s2 = '0') and (spec_user_aux_leds_swb_s1 = '1')) then
spec_user_aux_leds_o <= spec_user_aux_leds_int;
end if;
end if;
end process;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/modules/spec_user_interface/spec_user_interface.wb 0 → 100644
View file @ fa76945d
-- -*- Mode: LUA; tab-width: 4 -*-
-------------------------------------------------------------------------------
-- Title : SPEC User Interface
-- Project : SPEC-getting-started
-------------------------------------------------------------------------------
-- File : spec_user_interface.wb
-- Author : Javier D. Garcia-Lasheras
-- Created : 2014-02-24
-- Last update: 2014-02-24
-- Standard : wb (Wishbone Generator)
-------------------------------------------------------------------------------
-- Description:
-- Wishbone generator file used in the SPEC getting started project.
-- It contains a slave description for controlling the SPEC auxiliar interface.
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
-------------------------------------------------------------------------------
-- License : LGPLv3 or Later
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-02-24 1.0 jdgl Created
-------------------------------------------------------------------------------
peripheral {
name = "SPEC User Interface";
description = "A sample 32-bit general-purpose SPEC user interface port";
hdl_entity = "wb_slave_spec_user";
prefix = "spec_user";
reg {
name = "Control register";
description = "A register containing basic SPEC controls";
prefix = "ctrl";
field {
name = "PCB Version";
description = "This field accesses to the hard-wired 4 bits that indicate the PCB version";
prefix = "ver";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "spec_user_clk_i";
};
field {
name = "Front panel green LED";
description = "Control bit for the green LED placed on the SPEC front panel";
prefix = "led_green";
type = BIT;
size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "spec_user_clk_i";
};
field {
name = "Front panel red LED";
description = "Control bit for the red LED placed on the SPEC front panel";
prefix = "led_red";
type = BIT;
size = 1;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "spec_user_clk_i";
};
};
reg {
name = "Auxiliar interface";
description = "A register mapping the SPEC internal auxiliar interface";
prefix = "aux";
field {
name = "User Push-button 1";
description = "Status bit for the internal push-button 1";
prefix = "button1";
type = BIT;
size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "spec_user_clk_i";
};
field {
name = "User Push-button 2";
description = "Status bit for the internal push-button 2";
prefix = "button2";
type = BIT;
size = 1;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "spec_user_clk_i";
};
field {
name = "User Leds";
description = "Control field for the 4 internal auxiliar LEDs";
prefix = "leds";
type = SLV;
size = 4;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "spec_user_clk_i";
};
};
};
hdl/syn/spec/demo_user+dio/Manifest.py 0 → 100644
View file @ fa76945d
target = "xilinx"
action = "synthesis"
fetchto = "../../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_top.xise"
modules = { "local" :
[ "../../../top/spec/demo_user+dio",
"../../../ip_cores/general-cores",
"../../../ip_cores/gn4124-core",
"../../../modules/reset_generator",
"../../../modules/spec_user_interface",
"../../../modules/fmc_dio_ch5_ttl"]
}
hdl/syn/spec/demo_user/Manifest.py 0 → 100644
View file @ fa76945d
target = "xilinx"
action = "synthesis"
fetchto = "../../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_top"
syn_project = "spec_top.xise"
modules = { "local" :
[ "../../../top/spec/demo_user",
"../../../ip_cores/general-cores",
"../../../ip_cores/gn4124-core",
"../../../modules/reset_generator",
"../../../modules/spec_user_interface"]
}
hdl/top/spec/demo_user+dio/Manifest.py 0 → 100644
View file @ fa76945d
files = ["spec_top.vhd", "spec_top.ucf"]
modules = { "local" : ["../../../"] }
hdl/top/spec/demo_user+dio/spec_top.ucf 0 → 100644
View file @ fa76945d
#------------------------------------------------------------------------------
#-- Title : SPEC Top UCF (Demo User + DIO)
#-- Project : SPEC-getting-started
#------------------------------------------------------------------------------
#-- File : spec_top.ucf
#-- Author : Javier D. Garcia-Lasheras
#-- Created : 2014-02-24
#-- Last update: 2014-02-24
#-- Standard : Xilinx UCF
#------------------------------------------------------------------------------
#-- Description:
#-- Xilinx Constraints file for the Spec Demo User + DIO design.
#------------------------------------------------------------------------------
#-- Copyright (c) 2014 CERN
#------------------------------------------------------------------------------
#-- License : LGPLv3 or Later
#------------------------------------------------------------------------------
#-- Revisions :
#-- Date Version Author Description
#-- 2014-02-24 1.0 jdgl Created
#------------------------------------------------------------------------------
#################################################################
## Differential Clock input from the 125 MHz fixed reference ##
#################################################################
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
########################################
## Interface with the Gennum GN4124 ##
########################################
NET "cmp_gn4124_core/rst_*" TIG;
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
#--------------------------------
#-- Reset from Gennum GN4124 --
#--------------------------------
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "L_RST_N" TIG;
#------------------------------------
#-- Gennum GN4124 GPIO Interface --
#------------------------------------
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
#-----------------------------------------
#-- PCIe to local [Inbound Data] - RX --
#-----------------------------------------
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKN" TNM_NET = "p2l_clkn_grp";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" TNM_NET = "p2l_clkp_grp";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
#-------------------------------------
#-- Inbound Buffer Request/Status --
#-------------------------------------
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
#----------------------------------------------
#-- Local to Parallel [Outbound Data] - TX --
#----------------------------------------------
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
#------------------------------
#-- Outbound Buffer Status --
#------------------------------
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
###########################
## SPEC User Interface ##
###########################
NET "PCB_VER[0]" LOC = P5;
NET "PCB_VER[0]" IOSTANDARD = "LVCMOS15";
NET "PCB_VER[1]" LOC = P4;
NET "PCB_VER[1]" IOSTANDARD = "LVCMOS15";
NET "PCB_VER[2]" LOC = AA2;
NET "PCB_VER[2]" IOSTANDARD = "LVCMOS15";
NET "PCB_VER[3]" LOC = AA1;
NET "PCB_VER[3]" IOSTANDARD = "LVCMOS15";
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
NET "BUTTON1_I" LOC = C22;
NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "USER_LEDS[0]" LOC = G19;
NET "USER_LEDS[0]" IOSTANDARD = "LVCMOS18";
NET "USER_LEDS[1]" LOC = F20;
NET "USER_LEDS[1]" IOSTANDARD = "LVCMOS18";
NET "USER_LEDS[2]" LOC = F18;
NET "USER_LEDS[2]" IOSTANDARD = "LVCMOS18";
NET "USER_LEDS[3]" LOC = C20;
NET "USER_LEDS[3]" IOSTANDARD = "LVCMOS18";
###############################
## FMC Digital I/O 5Ch TTL ##
###############################
NET "dio_clk_p_i" LOC=L20;
NET "dio_clk_p_i" IOSTANDARD=LVDS_25;
NET "dio_clk_n_i" LOC=L22;
NET "dio_clk_n_i" IOSTANDARD=LVDS_25;
#----------------------
#-- FMC DIO Inputs --
#----------------------
NET "dio_p_i[4]" LOC =Y11;
NET "dio_p_i[4]" IOSTANDARD=LVDS_25;
NET "dio_n_i[4]" LOC =AB11;
NET "dio_n_i[4]" IOSTANDARD=LVDS_25;
NET "dio_p_i[3]" LOC =V7;
NET "dio_p_i[3]" IOSTANDARD=LVDS_25;
NET "dio_n_i[3]" LOC =W8;
NET "dio_n_i[3]" IOSTANDARD=LVDS_25;
NET "dio_p_i[2]" LOC =W12;
NET "dio_p_i[2]" IOSTANDARD=LVDS_25;
NET "dio_n_i[2]" LOC =Y12;
NET "dio_n_i[2]" IOSTANDARD=LVDS_25;
NET "dio_p_i[1]" LOC =R11;
NET "dio_p_i[1]" IOSTANDARD=LVDS_25;
NET "dio_n_i[1]" LOC =T11;
NET "dio_n_i[1]" IOSTANDARD=LVDS_25;
NET "dio_p_i[0]" LOC =C19;
NET "dio_p_i[0]" IOSTANDARD=LVDS_25;
NET "dio_n_i[0]" LOC =A19;
NET "dio_n_i[0]" IOSTANDARD=LVDS_25;
#-----------------------
#-- FMC DIO Outputs --
#-----------------------
NET "dio_p_o[4]" LOC= T8;
NET "dio_n_o[4]" LOC= U8;
NET "dio_p_o[4]" IOSTANDARD=LVDS_25;
NET "dio_n_o[4]" IOSTANDARD=LVDS_25;
NET "dio_p_o[3]" LOC= U9;
NET "dio_n_o[3]" LOC= V9;
NET "dio_p_o[3]" IOSTANDARD=LVDS_25;
NET "dio_n_o[3]" IOSTANDARD=LVDS_25;
NET "dio_p_o[2]" LOC= R9;
NET "dio_n_o[2]" LOC= R8;
NET "dio_p_o[2]" IOSTANDARD=LVDS_25;
NET "dio_n_o[2]" IOSTANDARD=LVDS_25;
NET "dio_p_o[1]" LOC= Y16;
NET "dio_n_o[1]" LOC= W15;
NET "dio_p_o[1]" IOSTANDARD=LVDS_25;
NET "dio_n_o[1]" IOSTANDARD=LVDS_25;
NET "dio_p_o[0]" LOC= W17;
NET "dio_n_o[0]" LOC= Y18;
NET "dio_p_o[0]" IOSTANDARD=LVDS_25;
NET "dio_n_o[0]" IOSTANDARD=LVDS_25;
#-----------------------------
#-- FMC DIO Output Enable --
#-----------------------------
NET "dio_oe_n_o[4]" LOC= AA6;
NET "dio_oe_n_o[3]" LOC= W10;
NET "dio_oe_n_o[2]" LOC= W11;
NET "dio_oe_n_o[1]" LOC= Y14;
NET "dio_oe_n_o[0]" LOC= V17;
NET "dio_oe_n_o[4]" IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[3]" IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[2]" IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[1]" IOSTANDARD=LVCMOS25;
NET "dio_oe_n_o[0]" IOSTANDARD=LVCMOS25;
#----------------------------------
#-- FMC DIO Termination Enable --
#----------------------------------
NET "dio_term_en_o[4]" LOC=AB7;
NET "dio_term_en_o[3]" LOC=Y7;
NET "dio_term_en_o[2]" LOC=AB6;
NET "dio_term_en_o[1]" LOC=AB5;
NET "dio_term_en_o[0]" LOC=W18;
NET "dio_term_en_o[4]" IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[3]" IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[2]" IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[1]" IOSTANDARD=LVCMOS25;
NET "dio_term_en_o[0]" IOSTANDARD=LVCMOS25;
#--------------------
#-- FMC DIO LEDs --
#--------------------
NET "dio_led_top_o" LOC= AA12;
NET "dio_led_top_o" IOSTANDARD=LVCMOS25;
NET "dio_led_bot_o" LOC= AB12;
NET "dio_led_bot_o" IOSTANDARD=LVCMOS25;
hdl/top/spec/demo_user+dio/spec_top.vhd 0 → 100644
View file @ fa76945d
-------------------------------------------------------------------------------
-- Title : SPEC Demo User + DIO
-- Project : SPEC-getting-started
-------------------------------------------------------------------------------
-- File : spec_top.vhd
-- Author : Javier D. Garcia-Lasheras
-- Created : 2014-02-24
-- Last update: 2014-02-24
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Very simple demo project using the SPEC card.
-- It contains a very simple example for controlling the auxiliar interface
-- and the basic features of the FMC DIO 5ch TTL module.
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
-------------------------------------------------------------------------------
-- License : LGPLv3 or Later
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-02-24 1.0 jdgl Created
-------------------------------------------------------------------------------
-- Memory map:
-- 0x00000000: User Interface
-- +0x00: Control register (PCB Version + Front Panel LEDs)
-- +0x04: Auxiliar Interface (Internal Pushbuttons + LEDs)
-- 0x00000100: Minimal DIO Interface
-- +0x00: DDR (Direction Register)
-- +0x04: PSR (Pin Status Register)
-- +0x08: PDR (Pin Data Value)
-- +0x0c: TERM (Pin Termination Register)
-- +0x10: SOPR (Set Output Pin Register)
-- +0x14: COPR (Set Output Pin Register)
-- +0x20: LEDS (LED Control Register)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.wishbone_pkg.all;
entity spec_top is
port
(
-------------------------------------------------------------------------
-- Differential Clock input from the 125 MHz fixed reference
-------------------------------------------------------------------------
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic; -- drives the PLL that generates System Clock
-------------------------------------------------------------------------
-- Interface with the Gennum GN4124
-------------------------------------------------------------------------
-- Reset from Gennum GN4124
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- Gennum GN4124 GPIO Interface
GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
-------------------------------------------------------------------------
-- SPEC User Interface
-------------------------------------------------------------------------
PCB_VER : in std_logic_vector(3 downto 0);
LED_RED : out std_logic;
LED_GREEN : out std_logic;
button1_i : in std_logic;
button2_i : in std_logic;
USER_LEDS : out std_logic_vector(3 downto 0);
-------------------------------------------------------------------------
-- FMC Digital I/O 5Ch TTL
-------------------------------------------------------------------------
dio_clk_p_i : in std_logic;
dio_clk_n_i : in std_logic;
dio_n_i : in std_logic_vector(4 downto 0);
dio_p_i : in std_logic_vector(4 downto 0);
dio_n_o : out std_logic_vector(4 downto 0);
dio_p_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_term_en_o : out std_logic_vector(4 downto 0);
dio_led_top_o : out std_logic;
dio_led_bot_o : out std_logic
);
end spec_top;
architecture rtl of spec_top is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component reset_generator
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
component gn4124_core is
port(
---------------------------------------------------------
-- Control and status
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
-- L2P Control
l2p_edb_o : out std_logic; -- Packet termination and discard
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i : in std_logic;
dma_reg_adr_i : in std_logic_vector(31 downto 0) := x"00000000";
dma_reg_dat_i : in std_logic_vector(31 downto 0) := x"00000000";
dma_reg_sel_i : in std_logic_vector(3 downto 0) := x"0";
dma_reg_stb_i : in std_logic := '0';
dma_reg_we_i : in std_logic := '0';
dma_reg_cyc_i : in std_logic := '0';
dma_reg_dat_o : out std_logic_vector(31 downto 0);
dma_reg_ack_o : out std_logic;
dma_reg_stall_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i : in std_logic;
csr_adr_o : out std_logic_vector(31 downto 0);
csr_dat_o : out std_logic_vector(31 downto 0);
csr_sel_o : out std_logic_vector(3 downto 0);
csr_stb_o : out std_logic;
csr_we_o : out std_logic;
csr_cyc_o : out std_logic;
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_sel_o : out std_logic_vector(3 downto 0);
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0) := x"00000000";
dma_ack_i : in std_logic := '0';
dma_stall_i : in std_logic := '0'
);
end component; -- gn4124_core
component wb_slave_spec_user is
port(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
spec_user_clk_i : in std_logic;
spec_user_ctrl_ver_i : in std_logic_vector(3 downto 0);
spec_user_ctrl_led_green_o : out std_logic;
spec_user_ctrl_led_red_o : out std_logic;
spec_user_aux_button1_i : in std_logic;
spec_user_aux_button2_i : in std_logic;
spec_user_aux_leds_o : out std_logic_vector(3 downto 0)
);
end component;
component fmc_dio_ch5_ttl is
port(
-- Whishbone Interface
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- FMC DIO 5ch TTL port
dio_clk_p_i : in std_logic;
dio_clk_n_i : in std_logic;
dio_n_i : in std_logic_vector(4 downto 0);
dio_p_i : in std_logic_vector(4 downto 0);
dio_n_o : out std_logic_vector(4 downto 0);
dio_p_o : out std_logic_vector(4 downto 0);
dio_oe_n_o : out std_logic_vector(4 downto 0);
dio_term_en_o : out std_logic_vector(4 downto 0);
dio_led_top_o : out std_logic;
dio_led_bot_o : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- Clock system signals
signal pllout_clk_sys : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_sys : std_logic;
-- Local reset
signal local_reset_n : std_logic;
-- Wishbone bus signals
signal genum_wb_out : t_wishbone_master_out;
signal genum_wb_in : t_wishbone_master_in;
signal fmc_dio_wb_out : t_wishbone_slave_out;
signal fmc_dio_wb_in : t_wishbone_slave_in;
signal spec_user_wb_out : t_wishbone_slave_out;
signal spec_user_wb_in : t_wishbone_slave_in;
constant zero_wb_in : t_wishbone_slave_in := (
cyc => '0',
stb => '0',
we => '0',
sel => (others => '0'),
dat => (others => '0'),
adr => (others => '0')
);
begin
------------------------------------------------------------------------------
-- Differential clock input buffer (from 125 MHz fixed reference)
------------------------------------------------------------------------------
cmp_pllrefclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- PLL System clock generator (62.5 MHz Output from 125 MHz input)
------------------------------------------------------------------------------
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
------------------------------------------------------------------------------
-- Global system clock buffer (distribute 62.5 MHz clock)
------------------------------------------------------------------------------
cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
------------------------------------------------------------------------------
-- Reset signal generator
------------------------------------------------------------------------------
U_Reset_Gen : reset_generator
port map (
clk_sys_i => clk_sys,
rst_pcie_n_a_i => L_RST_N,
rst_button_n_a_i => button1_i,
rst_n_o => local_reset_n);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => L_RST_N,
status_o => open,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
-- L2P Control
l2p_edb_o => L2P_EDB,
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => open,
irq_p_i => '0',
irq_p_o => GPIO(0),
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => clk_sys,
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => clk_sys,
csr_adr_o => genum_wb_out.adr,
csr_dat_o => genum_wb_out.dat,
csr_sel_o => genum_wb_out.sel,
csr_stb_o => genum_wb_out.stb,
csr_we_o => genum_wb_out.we,
csr_cyc_o => genum_wb_out.cyc,
csr_dat_i => genum_wb_in.dat,
csr_ack_i => genum_wb_in.ack,
csr_stall_i => genum_wb_in.stall,
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
dma_clk_i => clk_sys
--dma_adr_o => dma_adr,
--dma_dat_o => dma_dat_o,
--dma_sel_o => dma_sel,
--dma_stb_o => dma_stb,
--dma_we_o => dma_we,
--dma_cyc_o => dma_cyc,
--dma_dat_i => dma_dat_i,
--dma_ack_i => dma_ack,
--dma_stall_i => dma_stall
);
------------------------------------------------------------------------------
-- SPEC User Interface
------------------------------------------------------------------------------
U_spec_user_interface : wb_slave_spec_user
port map (
rst_n_i => L_RST_N,
clk_sys_i => clk_sys,
wb_adr_i => spec_user_wb_in.adr(0 downto 0),
wb_dat_i => spec_user_wb_in.dat,
wb_dat_o => spec_user_wb_out.dat,
wb_cyc_i => spec_user_wb_in.cyc,
wb_sel_i => spec_user_wb_in.sel,
wb_stb_i => spec_user_wb_in.stb,
wb_we_i => spec_user_wb_in.we,
wb_ack_o => spec_user_wb_out.ack,
spec_user_clk_i => clk_sys,
spec_user_ctrl_ver_i => PCB_VER,
spec_user_ctrl_led_green_o => LED_GREEN,
spec_user_ctrl_led_red_o => LED_RED,
spec_user_aux_button1_i => button1_i,
spec_user_aux_button2_i => button2_i,
spec_user_aux_leds_o => USER_LEDS
);
------------------------------------------------------------------------------
-- FMC Digital I/O 5Ch TTL
------------------------------------------------------------------------------
fmc_dio_port : fmc_dio_ch5_ttl
port map (
rst_n_i => L_RST_N,
clk_sys_i => clk_sys,
wb_adr_i => fmc_dio_wb_in.adr(3 downto 0),
wb_dat_i => fmc_dio_wb_in.dat,
wb_dat_o => fmc_dio_wb_out.dat,
wb_cyc_i => fmc_dio_wb_in.cyc,
wb_sel_i => fmc_dio_wb_in.sel,
wb_stb_i => fmc_dio_wb_in.stb,
wb_we_i => fmc_dio_wb_in.we,
wb_ack_o => fmc_dio_wb_out.ack,
wb_stall_o => fmc_dio_wb_out.stall,
-- FMC DIO 5ch TTL port
dio_clk_p_i => dio_clk_p_i,
dio_clk_n_i => dio_clk_n_i,
dio_n_i => dio_n_i,
dio_p_i => dio_p_i,
dio_n_o => dio_n_o,
dio_p_o => dio_p_o,
dio_oe_n_o => dio_oe_n_o,
dio_term_en_o => dio_term_en_o,
dio_led_top_o => dio_led_top_o,
dio_led_bot_o => dio_led_bot_o
);
------------------------------------------------------------------------------
-- Wishbone bus connection with simple multiplexing
------------------------------------------------------------------------------
slave_mux : process (clk_sys, L_RST_N)
begin -- process
-- Base offset for fmc_dio is 0x100 bytes
if (genum_wb_out.adr(6) = '0') then
spec_user_wb_in <= genum_wb_out;
fmc_dio_wb_in <= zero_wb_in;
genum_wb_in <= spec_user_wb_out;
else
spec_user_wb_in <= zero_wb_in;
fmc_dio_wb_in <= genum_wb_out;
genum_wb_in <= fmc_dio_wb_out;
end if;
end process;
end rtl;
hdl/top/spec/demo_user/Manifest.py 0 → 100644
View file @ fa76945d
files = ["spec_top.vhd", "spec_top.ucf"]
modules = { "local" : ["../../../"] }
hdl/top/spec/demo_user/spec_top.ucf 0 → 100644
View file @ fa76945d
#------------------------------------------------------------------------------
#-- Title : SPEC Top UCF (Demo User)
#-- Project : SPEC-getting-started
#------------------------------------------------------------------------------
#-- File : spec_top.ucf
#-- Author : Javier D. Garcia-Lasheras
#-- Created : 2014-02-24
#-- Last update: 2014-02-24
#-- Standard : Xilinx UCF
#------------------------------------------------------------------------------
#-- Description:
#-- Xilinx Constraints file for the Spec Demo User design.
#------------------------------------------------------------------------------
#-- Copyright (c) 2014 CERN
#------------------------------------------------------------------------------
#-- License : LGPLv3 or Later
#------------------------------------------------------------------------------
#-- Revisions :
#-- Date Version Author Description
#-- 2014-02-24 1.0 jdgl Created
#------------------------------------------------------------------------------
#################################################################
## Differential Clock input from the 125 MHz fixed reference ##
#################################################################
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
########################################
## Interface with the Gennum GN4124 ##
########################################
NET "cmp_gn4124_core/rst_*" TIG;
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
#--------------------------------
#-- Reset from Gennum GN4124 --
#--------------------------------
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "L_RST_N" TIG;
#------------------------------------
#-- Gennum GN4124 GPIO Interface --
#------------------------------------
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
#-----------------------------------------
#-- PCIe to local [Inbound Data] - RX --
#-----------------------------------------
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKN" TNM_NET = "p2l_clkn_grp";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" TNM_NET = "p2l_clkp_grp";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
#-------------------------------------
#-- Inbound Buffer Request/Status --
#-------------------------------------
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
#----------------------------------------------
#-- Local to Parallel [Outbound Data] - TX --
#----------------------------------------------
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
#------------------------------
#-- Outbound Buffer Status --
#------------------------------
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
###########################
## SPEC User Interface ##
###########################
NET "PCB_VER[0]" LOC = P5;
NET "PCB_VER[0]" IOSTANDARD = "LVCMOS15";
NET "PCB_VER[1]" LOC = P4;
NET "PCB_VER[1]" IOSTANDARD = "LVCMOS15";
NET "PCB_VER[2]" LOC = AA2;
NET "PCB_VER[2]" IOSTANDARD = "LVCMOS15";
NET "PCB_VER[3]" LOC = AA1;
NET "PCB_VER[3]" IOSTANDARD = "LVCMOS15";
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
NET "BUTTON1_I" LOC = C22;
NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "USER_LEDS[0]" LOC = G19;
NET "USER_LEDS[0]" IOSTANDARD = "LVCMOS18";
NET "USER_LEDS[1]" LOC = F20;
NET "USER_LEDS[1]" IOSTANDARD = "LVCMOS18";
NET "USER_LEDS[2]" LOC = F18;
NET "USER_LEDS[2]" IOSTANDARD = "LVCMOS18";
NET "USER_LEDS[3]" LOC = C20;
NET "USER_LEDS[3]" IOSTANDARD = "LVCMOS18";
hdl/top/spec/demo_user/spec_top.vhd 0 → 100644
View file @ fa76945d
-------------------------------------------------------------------------------
-- Title : SPEC Top (Demo User)
-- Project : SPEC-getting-started
-------------------------------------------------------------------------------
-- File : spec_top.vhd
-- Author : Javier D. Garcia-Lasheras
-- Created : 2014-02-24
-- Last update: 2014-02-24
-- Standard : VHDL
-------------------------------------------------------------------------------
-- Description:
-- Very simple demo project using the SPEC card.
-- It contains a very simple example for controlling the user/aux interface.
-------------------------------------------------------------------------------
-- Copyright (c) 2014 CERN
-------------------------------------------------------------------------------
-- License : LGPLv3 or Later
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-02-24 1.0 jdgl Created
-------------------------------------------------------------------------------
-- Memory map:
-- 0x00000000: User Interface
-- +0x00: Control register (PCB Version + Front Panel LEDs)
-- +0x04: Auxiliar Interface (Internal Pushbuttons + LEDs)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gn4124_core_pkg.all;
use work.gencores_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.wishbone_pkg.all;
entity spec_top is
port
(
-------------------------------------------------------------------------
-- Differential Clock input from the 125 MHz fixed reference
-------------------------------------------------------------------------
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic; -- drives the PLL that generates System Clock
-------------------------------------------------------------------------
-- Interface with the Gennum GN4124
-------------------------------------------------------------------------
-- Reset from Gennum GN4124
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- Gennum GN4124 GPIO Interface
GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
-------------------------------------------------------------------------
-- SPEC User Interface
-------------------------------------------------------------------------
PCB_VER : in std_logic_vector(3 downto 0);
LED_RED : out std_logic;
LED_GREEN : out std_logic;
button1_i : in std_logic;
button2_i : in std_logic;
USER_LEDS : out std_logic_vector(3 downto 0)
);
end spec_top;
architecture rtl of spec_top is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component reset_generator
port (
clk_sys_i : in std_logic;
rst_pcie_n_a_i : in std_logic;
rst_button_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
component gn4124_core is
port(
---------------------------------------------------------
-- Control and status
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
p2l_dframe_i : in std_logic; -- Receive Frame
p2l_valid_i : in std_logic; -- Receive Data Valid
-- P2L Control
p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
rx_error_o : out std_logic; -- Receive Error
vc_rdy_i : in std_logic_vector(1 downto 0); -- Virtual channel ready
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
l2p_dframe_o : out std_logic; -- Transmit Data Frame
l2p_valid_o : out std_logic; -- Transmit Data Valid
-- L2P Control
l2p_edb_o : out std_logic; -- Packet termination and discard
l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
tx_error_i : in std_logic; -- Transmit Error
---------------------------------------------------------
-- Interrupt interface
dma_irq_o : out std_logic_vector(1 downto 0); -- Interrupts sources to IRQ manager
irq_p_i : in std_logic; -- Interrupt request pulse from IRQ manager
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i : in std_logic;
dma_reg_adr_i : in std_logic_vector(31 downto 0) := x"00000000";
dma_reg_dat_i : in std_logic_vector(31 downto 0) := x"00000000";
dma_reg_sel_i : in std_logic_vector(3 downto 0) := x"0";
dma_reg_stb_i : in std_logic := '0';
dma_reg_we_i : in std_logic := '0';
dma_reg_cyc_i : in std_logic := '0';
dma_reg_dat_o : out std_logic_vector(31 downto 0);
dma_reg_ack_o : out std_logic;
dma_reg_stall_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i : in std_logic;
csr_adr_o : out std_logic_vector(31 downto 0);
csr_dat_o : out std_logic_vector(31 downto 0);
csr_sel_o : out std_logic_vector(3 downto 0);
csr_stb_o : out std_logic;
csr_we_o : out std_logic;
csr_cyc_o : out std_logic;
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0);
dma_sel_o : out std_logic_vector(3 downto 0);
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0) := x"00000000";
dma_ack_i : in std_logic := '0';
dma_stall_i : in std_logic := '0'
);
end component; -- gn4124_core
component wb_slave_spec_user is
port(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(0 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
spec_user_clk_i : in std_logic;
spec_user_ctrl_ver_i : in std_logic_vector(3 downto 0);
spec_user_ctrl_led_green_o : out std_logic;
spec_user_ctrl_led_red_o : out std_logic;
spec_user_aux_button1_i : in std_logic;
spec_user_aux_button2_i : in std_logic;
spec_user_aux_leds_o : out std_logic_vector(3 downto 0)
);
end component;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
-- Clock system signals
signal pllout_clk_sys : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal clk_125m_pllref : std_logic;
signal clk_sys : std_logic;
-- Local reset
signal local_reset_n : std_logic;
-- Wishbone bus signals
signal genum_wb_out : t_wishbone_master_out;
signal genum_wb_in : t_wishbone_master_in;
signal spec_user_wb_out : t_wishbone_slave_out;
signal spec_user_wb_in : t_wishbone_slave_in;
begin
------------------------------------------------------------------------------
-- Differential clock input buffer (from 125 MHz fixed reference)
------------------------------------------------------------------------------
cmp_pllrefclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
------------------------------------------------------------------------------
-- PLL System clock generator (62.5 MHz Output from 125 MHz input)
------------------------------------------------------------------------------
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 16,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
------------------------------------------------------------------------------
-- Global system clock buffer (distribute 62.5 MHz clock)
------------------------------------------------------------------------------
cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
------------------------------------------------------------------------------
-- Reset signal generator
------------------------------------------------------------------------------
U_Reset_Gen : reset_generator
port map (
clk_sys_i => clk_sys,
rst_pcie_n_a_i => L_RST_N,
rst_button_n_a_i => button1_i,
rst_n_o => local_reset_n);
------------------------------------------------------------------------------
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
port map
(
---------------------------------------------------------
-- Control and status
rst_n_a_i => L_RST_N,
status_o => open,
---------------------------------------------------------
-- P2L Direction
--
-- Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
vc_rdy_i => VC_RDY,
---------------------------------------------------------
-- L2P Direction
--
-- Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
-- L2P Control
l2p_edb_o => L2P_EDB,
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
---------------------------------------------------------
-- Interrupt interface
dma_irq_o => open,
irq_p_i => '0',
irq_p_o => GPIO(0),
---------------------------------------------------------
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => clk_sys,
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i => clk_sys,
csr_adr_o => genum_wb_out.adr,
csr_dat_o => genum_wb_out.dat,
csr_sel_o => genum_wb_out.sel,
csr_stb_o => genum_wb_out.stb,
csr_we_o => genum_wb_out.we,
csr_cyc_o => genum_wb_out.cyc,
csr_dat_i => genum_wb_in.dat,
csr_ack_i => genum_wb_in.ack,
csr_stall_i => genum_wb_in.stall,
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
dma_clk_i => clk_sys
--dma_adr_o => dma_adr,
--dma_dat_o => dma_dat_o,
--dma_sel_o => dma_sel,
--dma_stb_o => dma_stb,
--dma_we_o => dma_we,
--dma_cyc_o => dma_cyc,
--dma_dat_i => dma_dat_i,
--dma_ack_i => dma_ack,
--dma_stall_i => dma_stall
);
------------------------------------------------------------------------------
-- SPEC User Interface
------------------------------------------------------------------------------
U_spec_user_interface : wb_slave_spec_user
port map (
rst_n_i => L_RST_N,
clk_sys_i => clk_sys,
wb_adr_i => spec_user_wb_in.adr(0 downto 0),
wb_dat_i => spec_user_wb_in.dat,
wb_dat_o => spec_user_wb_out.dat,
wb_cyc_i => spec_user_wb_in.cyc,
wb_sel_i => spec_user_wb_in.sel,
wb_stb_i => spec_user_wb_in.stb,
wb_we_i => spec_user_wb_in.we,
wb_ack_o => spec_user_wb_out.ack,
spec_user_clk_i => clk_sys,
spec_user_ctrl_ver_i => PCB_VER,
spec_user_ctrl_led_green_o => LED_GREEN,
spec_user_ctrl_led_red_o => LED_RED,
spec_user_aux_button1_i => button1_i,
spec_user_aux_button2_i => button2_i,
spec_user_aux_leds_o => USER_LEDS
);
------------------------------------------------------------------------------
-- Wishbone bus connection
------------------------------------------------------------------------------
spec_user_wb_in <= genum_wb_out;
genum_wb_in <= spec_user_wb_out;
end rtl;
sw/python/.gitignore 0 → 100644
View file @ fa76945d
*.*~
*.pyc
__pycache__/
sw/python/spec_demo_user.py 0 → 100644
View file @ fa76945d
'''
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
'''
__author__ = "Javier D. Garcia-Lasheras"
__copyright__ = "Copyright 2014, CERN"
__license__ = "GPLv3 or later"
__version__ = "1.0"
__maintainer__ = "Javier D. Garcia-Lasheras"
__email__ = "javier@garcialasheras.com"
__status__ = "Development"
from spec_libc import *
class SpecDemoUser(Spec):
'''Simple demo application demonstrating the use of Spec class.
This is part of the getting started with the SPEC project.
By creating a SpecDemoUser object, access to the basic functions
covered in the gateware HDL Spec Demo User is granted.
In this way, the SPEC FPGA must be programmed with the specific bitstream.
For this purpose, use the specLoadBitstream() method inherited from Spec.
'''
def __init__(self, bus=-1, dev=-1, libc='/usr/lib/libspec.so'):
Spec.__init__(self, bus=bus, dev=dev, libc=libc)
self.userAddressMap = {
'control': 0x0,
'auxiliar': 0x4,
}
self.userControlOffsets = {
'PCBVersion': 0,
'GreenLED': 4,
'RedLED': 5,
}
self.userAuxiliarOffsets = {
'Button1': 0,
'Button2': 1,
'AuxLEDs': 2,
}
def specGetPCBVersion(self):
'''Return the SPEC PCB version as an integer value.'''
register = self.specReadL(0x0, hexformat=False)
register = int(register % 16)
return register
# Green LED Controls
def specGetGreenLED(self):
'''Test the status of the SPEC Front Panel Green LED.
returns a nonzero result if the LED is ON, 0 if the LED is OFF.'''
address = self.userAddressMap['control']
offset = self.userControlOffsets['GreenLED']
return self.specTestBit(address, offset)
def specSetGreenLED(self):
'''Set to ON the SPEC Front Panel Green LED.'''
address = self.userAddressMap['control']
offset = self.userControlOffsets['GreenLED']
self.specSetBit(address, offset)
def specClearGreenLED(self):
'''Clear to OFF the SPEC Front Panel Green LED.'''
address = self.userAddressMap['control']
offset = self.userControlOffsets['GreenLED']
self.specClearBit(address, offset)
def specToggleGreenLED(self):
'''Toggle/change the SPEC Front Panel Green LED.'''
address = self.userAddressMap['control']
offset = self.userControlOffsets['GreenLED']
self.specToggleBit(address, offset)
# Red LED Controls
def specGetRedLED(self):
'''Test the status of the SPEC Front Panel Red LED.
returns a nonzero result if the LED is ON, 0 if the LED is OFF.'''
address = self.userAddressMap['control']
offset = self.userControlOffsets['RedLED']
return self.specTestBit(address, offset)
def specSetRedLED(self):
'''Set to ON the SPEC Front Panel Red LED.'''
address = self.userAddressMap['control']
offset = self.userControlOffsets['RedLED']
self.specSetBit(address, offset)
def specClearRedLED(self):
'''Clear to OFF the SPEC Front Panel Red LED.'''
address = self.userAddressMap['control']
offset = self.userControlOffsets['RedLED']
self.specClearBit(address, offset)
def specToggleRedLED(self):
'''Toggle/change the SPEC Front Panel Red LED.'''
address = self.userAddressMap['control']
offset = self.userControlOffsets['RedLED']
self.specToggleBit(address, offset)
# Auxiliar pushbuttons
def specGetButton1(self):
'''Test the state of the internal auxiliar Button1.
Return 0 when pressed and nonzero when released.'''
address = self.userAddressMap['auxiliar']
offset = self.userAuxiliarOffsets['Button1']
return self.specTestBit(address, offset)
def specGetButton2(self):
'''Test the state of the internal auxiliar Button2.
Return 0 when pressed and nonzero when released.'''
address = self.userAddressMap['auxiliar']
offset = self.userAuxiliarOffsets['Button2']
return self.specTestBit(address, offset)
# Auxiliar LEDs
def specGetAuxLEDs(self, hexformat=True):
'''Return the hex value corresponding to the four auxiliar LEDs.
If hexformat=True, the returned value is a string in hex format.
Note that the Auxiliar LEDs are active low.'''
address = self.userAddressMap['auxiliar']
offset = self.userAuxiliarOffsets['AuxLEDs']
register = self.specReadL(address, hexformat=False)
register = register >> offset
mask = 0xf
register = register & mask
if hexformat:
register = hex(register)
return register
def specSetAuxLEDs(self, value):
'''Set the hex value corresponding to the four auxiliar LEDs.
Note that the Auxiliar LEDs are active low.'''
address = self.userAddressMap['auxiliar']
offset = self.userAuxiliarOffsets['AuxLEDs']
register = self.specReadL(address, hexformat=False)
mask = ~(0xf << offset)
register = register & mask
mask = value << offset
register = register | mask
self.specWriteL(address, register)
sw/python/spec_demo_user_dio.py 0 → 100644
View file @ fa76945d
'''
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
'''
__author__ = "Javier D. Garcia-Lasheras"
__copyright__ = "Copyright 2014, CERN"
__license__ = "GPLv3 or later"
__version__ = "1.0"
__maintainer__ = "Javier D. Garcia-Lasheras"
__email__ = "javier@garcialasheras.com"
__status__ = "Development"
from spec_demo_user import *
class SpecDemoUserDIO(SpecDemoUser):
'''Simple demo application demonstrating the use of Spec class.
This is part of the getting started with the SPEC project.
By creating a SpecDemoUserDIO object, access to the basic functions
covered in the gateware HDL Spec Demo User DIO is granted.
In this way, the SPEC FPGA must be programmed with the specific bitstream.
For this purpose, use the specLoadBitstream() method inherited from Spec.
'''
def __init__(self, bus=-1, dev=-1, libc='/usr/lib/libspec.so'):
SpecDemoUser.__init__(self, bus=bus, dev=dev, libc=libc)
self.dioBaseAddress = 0x100
self.dioAddressMap = {
'DDR': 0x00,
'PSR': 0x04,
'PDR': 0x08,
'TERM': 0x0C,
'SOPR': 0x10,
'COPR': 0x14,
'LED': 0x20,
}
self.dioLEDOffsets = {
'Bottom': 0,
'Top': 1,
}
# DIO Bottom LED Controls
def dioGetBottomLED(self):
'''Test the status of the DIO Front Panel Bottom LED.
returns a nonzero result if the LED is ON, 0 if the LED is OFF.'''
address = self.dioAddressMap['LED'] + self.dioBaseAddress
offset = self.dioLEDOffsets['Bottom']
return self.specTestBit(address, offset)
def dioSetBottomLED(self):
'''Set to ON the DIO Front Panel Bottom LED.'''
address = self.dioAddressMap['LED'] + self.dioBaseAddress
offset = self.dioLEDOffsets['Bottom']
self.specSetBit(address, offset)
def dioClearBottomLED(self):
'''Clear to OFF the DIO Front Panel Bottom LED.'''
address = self.dioAddressMap['LED'] + self.dioBaseAddress
offset = self.dioLEDOffsets['Bottom']
self.specClearBit(address, offset)
def dioToggleBottomLED(self):
'''Toggle/change the DIO Front Panel Bottom LED.'''
address = self.dioAddressMap['LED'] + self.dioBaseAddress
offset = self.dioLEDOffsets['Bottom']
self.specToggleBit(address, offset)
# DIO Top LED Controls
def dioGetTopLED(self):
'''Test the status of the DIO Front Panel Top LED.
returns a nonzero result if the LED is ON, 0 if the LED is OFF.'''
address = self.dioAddressMap['LED'] + self.dioBaseAddress
offset = self.dioLEDOffsets['Top']
return self.specTestBit(address, offset)
def dioSetTopLED(self):
'''Set to ON the DIO Front Panel Top LED.'''
address = self.dioAddressMap['LED'] + self.dioBaseAddress
offset = self.dioLEDOffsets['Top']
self.specSetBit(address, offset)
def dioClearTopLED(self):
'''Clear to OFF the DIO Front Panel Top LED.'''
address = self.dioAddressMap['LED'] + self.dioBaseAddress
offset = self.dioLEDOffsets['Top']
self.specClearBit(address, offset)
def dioToggleTopLED(self):
'''Toggle/change the DIO Front Panel Top LED.'''
address = self.dioAddressMap['LED'] + self.dioBaseAddress
offset = self.dioLEDOffsets['Top']
self.specToggleBit(address, offset)
# DIO pin controls
def dioWriteDirection(self, value):
'''Set the DIO pin directions as a 5 chars string.
Write char 1 for output and 0 for input.
e.g. Pin 5 output, others input: value = '10000'.'''
address = self.dioAddressMap['DDR'] + self.dioBaseAddress
self.specWriteL(address, int(value, 2))
def dioReadDirection(self):
'''Return the DIO pin directions as a 5 chars string.
Read char 1 for output and 0 for input.
e.g. Pin 5 output, others input: return '10000'.'''
address = self.dioAddressMap['DDR'] + self.dioBaseAddress
register = self.specReadL(address, hexformat=False)
return format(register, '05b')
def dioReadValue(self):
'''Return the DIO pin values as a 5 chars string.
Read char 1 for HIGH and 0 for LOW.
e.g. Pin 5 HIGH, others LOW: return '10000'.'''
address = self.dioAddressMap['PSR'] + self.dioBaseAddress
register = self.specReadL(address, hexformat=False)
return format(register, '05b')
def dioWriteValue(self, value):
'''Set the DIO pin values as a 5 chars string.
Write char 1 for HIGH and 0 for LOW.
e.g. Pin 5 HIGH, others LOW: value = '10000'.'''
address = self.dioAddressMap['PDR'] + self.dioBaseAddress
self.specWriteL(address, int(value, 2))
def dioWriteTermination(self, value):
'''Set the DIO pin termination resistor as a 5 chars string.
Write char 1 for termination ON and 0 for termination OFF.
e.g. Pin 5 termination ON, others termination OFF: value = '10000'.'''
address = self.dioAddressMap['TERM'] + self.dioBaseAddress
self.specWriteL(address, int(value, 2))
def dioReadTermination(self):
'''Return the DIO pin termination resistor as a 5 chars string.
Read char 1 for termination ON and 0 for termination OFF.
e.g. Pin 5 termination ON, others termination OFF: return '10000'.'''
address = self.dioAddressMap['TERM'] + self.dioBaseAddress
register = self.specReadL(address, hexformat=False)
return format(register, '05b')
def dioSetOutput(self, value):
'''Set to 1 the selected DIO pins as a 5 chars string.
Write char 1 for selected and 0 for unchanged.
e.g. Pin 5 set, others unchanged: value = '10000'.'''
address = self.dioAddressMap['SOPR'] + self.dioBaseAddress
self.specWriteL(address, int(value, 2))
def dioClearOutput(self, value):
'''Clear to 0 the selected DIO pins as a 5 chars string.
Write char 1 for selected and 0 for unchanged.
e.g. Pin 5 clear, others unchanged: value = '10000'.'''
address = self.dioAddressMap['COPR'] + self.dioBaseAddress
self.specWriteL(address, int(value, 2))
sw/python/spec_libc.py 0 → 100644
View file @ fa76945d
'''
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
'''
__author__ = "Javier D. Garcia-Lasheras"
__copyright__ = "Copyright 2014, CERN"
__license__ = "GPLv3 or later"
__version__ = "1.0"
__maintainer__ = "Javier D. Garcia-Lasheras"
__email__ = "javier@garcialasheras.com"
__status__ = "Development"
from ctypes import *
import os, errno, re, sys, struct
class SpecCard(Structure):
''' This Python structure matches with
the spec_private C one in speclib.c'''
_fields_ = [
("bar0", c_void_p),
("bar4", c_void_p),
("vuart_base", c_uint),
]
class Spec():
"""A Class that creates SPEC objects. This includes basic controls
and methods in order to handle a PCIe attached SPEC board.
Access to a valid libspec.so is mandatory for a proper operation.
NOTE: user write/access permission to the SPEC dev is mandatory.
Attributes:
bus, dev bus and device for the requested SPEC device.
If one (or both) parameters are < 0,
takes first available card.
libc Path to a valid libspec.so shared library.
If empty, it points to /usr/lib/libspec.so
"""
def __init__(self, bus=-1, dev=-1, libc='/usr/lib/libspec.so'):
if not os.path.isfile(libc):
print('ERROR: libspec.so library not found')
raise Exception()
# Load library
self.speclib = CDLL(libc)
# redefine return types
self.speclib.spec_open.restype = POINTER(SpecCard)
self.speclib.spec_readl.restype = c_uint
self.my_card = self.speclib.spec_open(c_int(bus), c_int(dev))
print('a new SPEC object has been created')
def __del__(self):
'''Destroying the SPEC card object'''
self.speclib.spec_close(self.my_card)
print('The SPEC object has been destroyed')
def specLoadBitstream(self, bitstream):
'''Load a new bitstream into the SPEC throughout GN4124 interface.
bitstream is the path to the .bin bitstream that must be loaded.
'''
if os.path.isfile(bitstream):
print('the bitstream has been found...')
gateware = create_string_buffer(bitstream.encode('utf-8'))
gateware_ok = self.speclib.spec_load_bitstream(
self.my_card, byref(gateware))
if gateware_ok != 0:
print('the bitstream has been successfully loaded')
else:
print('the bitstream loading has failed')
else:
print('cannot find the bitstream!!!')
# 32 bit register operations in the Wishbone addressing space
def specWriteL(self, address, data):
'''Write a 32 bit integer data into the register at address'''
self.speclib.spec_writel(self.my_card, c_uint(data), c_uint(address))
def specReadL(self, address, hexformat=True):
'''Read a 32 bit integer data from the register at address.
Return an hex string if hexformat=True, an integer otherwise'''
data = self.speclib.spec_readl(self.my_card, c_uint(address))
if hexformat:
data = hex(data)
return data
# bitwise register operations in the Wishbone addressing space
def specTestBit(self, address, offset):
'''Test the bit placed at offset in the register at address.
returns a nonzero result, 2**offset, if the bit is 1'''
register = self.specReadL(address, hexformat=False)
mask = 1 << offset
return(register & mask)
def specSetBit(self, address, offset):
'''Set to 1 the bit placed at offset in the register at address'''
register = self.specReadL(address, hexformat=False)
mask = 1 << offset
self.specWriteL(address, register | mask)
def specClearBit(self, address, offset):
'''Clear to 0 the bit placed at offset in the register at address'''
register = self.specReadL(address, hexformat=False)
mask = ~(1 << offset)
self.specWriteL(address, register & mask)
def specToggleBit(self, address, offset):
'''Toggle/invert the bit placed at offset in the register at address'''
register = self.specReadL(address, hexformat=False)
mask = 1 << offset
self.specWriteL(address, register ^ mask)
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