Commit 63136820 authored by Maciej Lipinski's avatar Maciej Lipinski

[tmp-btrain] tool to ctr/dbg wr_streamers and btrain

this tool needs to be later put in a proper repo/place. but for the
time being it was the easiest to have it here.
parent 5f15d26e
......@@ -19,6 +19,7 @@ LIBSHARED = libspec.so
PROGS = spec-cl spec-fwloader spec-vuart specmem
PROGS += wr-dio-cmd wr-dio-pps wr-dio-agent wr-dio-ruler
PROGS += stamp-frame
PROGS += wr_transmission
all: $(LIB) $(PROGS) $(LIBSHARED)
......
/*
Register definitions for slave core: WR Btrain transmission control
* File : WRBtrain.h
* Author : auto-generated by wbgen2 from WRBtrain_wb.wb
* Created : Tue Nov 29 00:33:02 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE WRBtrain_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_WRBTRAIN_WB_WB
#define __WBGEN2_REGDEFS_WRBTRAIN_WB_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Status and ctontrol register */
/* definitions for field: Transmit single frame in reg: Status and ctontrol register */
#define WRBTRAIN_SCR_TX_SINGLE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Debug mode in reg: Status and ctontrol register */
#define WRBTRAIN_SCR_TX_DBG_MASK WBGEN2_GEN_MASK(1, 2)
#define WRBTRAIN_SCR_TX_DBG_SHIFT 1
#define WRBTRAIN_SCR_TX_DBG_W(value) WBGEN2_GEN_WRITE(value, 1, 2)
#define WRBTRAIN_SCR_TX_DBG_R(reg) WBGEN2_GEN_READ(reg, 1, 2)
/* definitions for field: Invert RX valid polarity in reg: Status and ctontrol register */
#define WRBTRAIN_SCR_RX_VALID_POL_INV WBGEN2_GEN_MASK(8, 1)
/* definitions for field: Dummy in reg: Status and ctontrol register */
#define WRBTRAIN_SCR_DUMMY_MASK WBGEN2_GEN_MASK(16, 16)
#define WRBTRAIN_SCR_DUMMY_SHIFT 16
#define WRBTRAIN_SCR_DUMMY_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define WRBTRAIN_SCR_DUMMY_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Transmission period */
/* definitions for field: Period in clock cylces (16ns). When the value is not zero, frames are sent with that period. in reg: Transmission period */
#define WRBTRAIN_TX_PERIOD_VALUE_MASK WBGEN2_GEN_MASK(0, 32)
#define WRBTRAIN_TX_PERIOD_VALUE_SHIFT 0
#define WRBTRAIN_TX_PERIOD_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WRBTRAIN_TX_PERIOD_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Rx output data valid delay and period */
/* definitions for field: Output data valid period in reg: Rx output data valid delay and period */
#define WRBTRAIN_RX_OUT_DATA_TIME_VALID_MASK WBGEN2_GEN_MASK(0, 16)
#define WRBTRAIN_RX_OUT_DATA_TIME_VALID_SHIFT 0
#define WRBTRAIN_RX_OUT_DATA_TIME_VALID_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define WRBTRAIN_RX_OUT_DATA_TIME_VALID_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Output data delay in reg: Rx output data valid delay and period */
#define WRBTRAIN_RX_OUT_DATA_TIME_DELAY_MASK WBGEN2_GEN_MASK(16, 16)
#define WRBTRAIN_RX_OUT_DATA_TIME_DELAY_SHIFT 16
#define WRBTRAIN_RX_OUT_DATA_TIME_DELAY_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define WRBTRAIN_RX_OUT_DATA_TIME_DELAY_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: SimBval: control subcycles */
/* definitions for field: Cycle Length in reg: SimBval: control subcycles */
#define WRBTRAIN_SIMB_CTRL_CLEN_MASK WBGEN2_GEN_MASK(0, 4)
#define WRBTRAIN_SIMB_CTRL_CLEN_SHIFT 0
#define WRBTRAIN_SIMB_CTRL_CLEN_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define WRBTRAIN_SIMB_CTRL_CLEN_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for field: Sub-cycle ID in reg: SimBval: control subcycles */
#define WRBTRAIN_SIMB_CTRL_SCID_MASK WBGEN2_GEN_MASK(4, 4)
#define WRBTRAIN_SIMB_CTRL_SCID_SHIFT 4
#define WRBTRAIN_SIMB_CTRL_SCID_W(value) WBGEN2_GEN_WRITE(value, 4, 4)
#define WRBTRAIN_SIMB_CTRL_SCID_R(reg) WBGEN2_GEN_READ(reg, 4, 4)
/* definitions for field: Cycle maximum length in reg: SimBval: control subcycles */
#define WRBTRAIN_SIMB_CTRL_CMAXLEN_MASK WBGEN2_GEN_MASK(8, 4)
#define WRBTRAIN_SIMB_CTRL_CMAXLEN_SHIFT 8
#define WRBTRAIN_SIMB_CTRL_CMAXLEN_W(value) WBGEN2_GEN_WRITE(value, 8, 4)
#define WRBTRAIN_SIMB_CTRL_CMAXLEN_R(reg) WBGEN2_GEN_READ(reg, 8, 4)
/* definitions for register: SimBval: Sub-cycle lenght */
/* definitions for field: Lenght in sent frames, i.e. the in reg: SimBval: Sub-cycle lenght */
#define WRBTRAIN_BSIM_SCYC_LEN_VAL_MASK WBGEN2_GEN_MASK(0, 32)
#define WRBTRAIN_BSIM_SCYC_LEN_VAL_SHIFT 0
#define WRBTRAIN_BSIM_SCYC_LEN_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define WRBTRAIN_BSIM_SCYC_LEN_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: SimBval: Sub-cycle increment */
/* definitions for field: Signed value that is added to the Bvalue each time Btrain frame is transmitted. in reg: SimBval: Sub-cycle increment */
#define WRBTRAIN_BSIM_SCYC_INC_VAL_MASK WBGEN2_GEN_MASK(0, 16)
#define WRBTRAIN_BSIM_SCYC_INC_VAL_SHIFT 0
#define WRBTRAIN_BSIM_SCYC_INC_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define WRBTRAIN_BSIM_SCYC_INC_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* [0x0]: REG Status and ctontrol register */
#define WRBTRAIN_REG_SCR 0x00000000
/* [0x4]: REG Transmission period */
#define WRBTRAIN_REG_TX_PERIOD 0x00000004
/* [0x8]: REG Rx output data valid delay and period */
#define WRBTRAIN_REG_RX_OUT_DATA_TIME 0x00000008
/* [0xc]: REG SimBval: control subcycles */
#define WRBTRAIN_REG_SIMB_CTRL 0x0000000c
/* [0x10]: REG SimBval: Sub-cycle lenght */
#define WRBTRAIN_REG_BSIM_SCYC_LEN 0x00000010
/* [0x14]: REG SimBval: Sub-cycle increment */
#define WRBTRAIN_REG_BSIM_SCYC_INC 0x00000014
#endif
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