Skip to content

S
Simple PCIe FMC carrier SPEC - Software
Commit dc7a4c3c authored by Alessandro Rubini's avatar Alessandro Rubini
Browse files
Options

wbgen-regs: copied from wr-switch-sw (v3.0) 

This is an exact copy of the register definitions from the wr-switch-sw
project.  The two projects share the same WR ptp-core, so most of this
applies here as well.
parent 24da69e3
Hide whitespace changes
Inline Side-by-side
Showing with 5428 additions and 0 deletions
kernel/wbgen-regs/Makefile 0 → 100644
View file @ dc7a4c3c
# This Makefile is used to reproduce the headers from svn checkout.
# You need to have "wbgen2" in your command search path and the white-rabbit
# repos (wr-cores and wr-switch-hdl) Git checkout in $REPOS.
# Since this is only meant to be used by me (or Tom) no serious checking is done.
# List of input files in Git checkout
MODULES_WRS ?= $(REPOS)/wr-switch-hdl/modules
MODULES_WRC ?= $(REPOS)/wr-cores/modules
#SPECS = $(HW_REPO)/trunk/documentation/specifications
WB_ENDPOINT = $(MODULES_WRC)/wr_endpoint/ep_wishbone_controller.wb
WB_MDIO = $(MODULES_WRC)/wr_endpoint/pcs_regs.wb
WB_PPSG = $(MODULES_WRC)/wr_pps_gen/pps_gen_wb.wb
WB_TSTAMP = $(MODULES_WRS)/wrsw_txtsu/wrsw_txtsu.wb
WB_RTU = $(MODULES_WRS)/wrsw_rtu/rtu_wishbone_slave.wb
WB_NIC = $(MODULES_WRS)/wrsw_nic/wr_nic.wb
WB_SOFTPLL = $(MODULES_WRC)/wr_softpll_ng/spll_wb_slave.wb
HEADERS = endpoint-regs.h endpoint-mdio.h ppsg-regs.h tstamp-regs.h rtu-regs.h \
nic-regs.h softpll-regs.h
WBINPUT = $(HEADERS:.h=wb)
# No default, for people who types "make" everywhere (like me)
all:
@echo "This is for developer's use, see Makefile for details"
exit 1
# The headers rule regenerates headers from local wb files
headers: $(HEADERS)
%.h: %.wb
wbgen2 --cstyle=struct --co=$@ $<
sed -i 's,#include <inttypes.h>,#ifdef __KERNEL__\n#include <linux/types.h>\n#else\n#include <stdint.h>\n#endif\n,' $@
sed -i '/ Created *: .*20[0-9][0-9]$$/ d' $@
sed -i 's/-REGS_WB//' $@
# The wbinput rule just copies here stuff from svn.
# Do it silent so errors stand out
wbinput:
@cp $(WB_ENDPOINT) endpoint-regs.wb
@cp $(WB_MDIO) endpoint-mdio.wb
@cp $(WB_PPSG) ppsg-regs.wb
@cp $(WB_TSTAMP) tstamp-regs.wb
@cp $(WB_RTU) rtu-regs.wb
@cp $(WB_NIC) nic-regs.wb
@cp $(WB_SOFTPLL) softpll-regs.wb
@echo "Copied input files from subversions to local directory"
kernel/wbgen-regs/README 0 → 100644
View file @ dc7a4c3c
The headers have been derived from what is in svn:
documentation/specifications/hdlspec/memory_map/
In that directory you find the html generated from the wb files.
Here I import the relevant headers. The overall register
map is in ../nic/nic-hardware.h .
The .wb files whence the headers are generated come from different
plases in the white rabbit svn. To ease myself I wrote this in
the Makefile. You can "make wbinput" to get a fresh copy of them,
provided you have SVN set in your environment (point to the root
checkout, before "trunk" subdirectory). If unset or wrong, cp fails.
With "make headers" you can regenerate the headers from the wb input
files. Each generated file is postprocesses with sed to fix these
issues:
* generated files include <inttypes.h> as they use uint32_t. We want
<linux/types.h> instead, as no <inttypes.h> nor <stdint.h> is there
* generated files include the date of creation. This brings to noise
in the "git diff" or plain "diff", so I'd better have no date.
* creation of "#ifdef __THIS_HEADER__" fails on the dash, so I remove
the dash and trailing part with sed (as of writing, it has issues with
pathnames too, this is one the reasons why I copy the wb here first).
kernel/wbgen-regs/endpoint-mdio.h 0 → 100644
View file @ dc7a4c3c
/*
Register definitions for slave core: WR Endpoint 1000base-X TBI PCS register block
* File : endpoint-mdio.h
* Author : auto-generated by wbgen2 from endpoint-mdio.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE endpoint-mdio.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_ENDPOINT-MDIO_WB
#define __WBGEN2_REGDEFS_ENDPOINT-MDIO_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: MDIO Control Register */
/* definitions for field: Reserved in reg: MDIO Control Register */
#define MDIO_MCR_RESV_MASK WBGEN2_GEN_MASK(0, 5)
#define MDIO_MCR_RESV_SHIFT 0
#define MDIO_MCR_RESV_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define MDIO_MCR_RESV_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Unidirectional Enable in reg: MDIO Control Register */
#define MDIO_MCR_UNI_EN WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Speed Selection (MSB) in reg: MDIO Control Register */
#define MDIO_MCR_SPEED1000_MASK WBGEN2_GEN_MASK(6, 1)
#define MDIO_MCR_SPEED1000_SHIFT 6
#define MDIO_MCR_SPEED1000_W(value) WBGEN2_GEN_WRITE(value, 6, 1)
#define MDIO_MCR_SPEED1000_R(reg) WBGEN2_GEN_READ(reg, 6, 1)
/* definitions for field: Collision Test in reg: MDIO Control Register */
#define MDIO_MCR_CTST_MASK WBGEN2_GEN_MASK(7, 1)
#define MDIO_MCR_CTST_SHIFT 7
#define MDIO_MCR_CTST_W(value) WBGEN2_GEN_WRITE(value, 7, 1)
#define MDIO_MCR_CTST_R(reg) WBGEN2_GEN_READ(reg, 7, 1)
/* definitions for field: Duplex Mode in reg: MDIO Control Register */
#define MDIO_MCR_FULLDPLX_MASK WBGEN2_GEN_MASK(8, 1)
#define MDIO_MCR_FULLDPLX_SHIFT 8
#define MDIO_MCR_FULLDPLX_W(value) WBGEN2_GEN_WRITE(value, 8, 1)
#define MDIO_MCR_FULLDPLX_R(reg) WBGEN2_GEN_READ(reg, 8, 1)
/* definitions for field: Restart Auto-Negotiation in reg: MDIO Control Register */
#define MDIO_MCR_ANRESTART WBGEN2_GEN_MASK(9, 1)
/* definitions for field: Isolate in reg: MDIO Control Register */
#define MDIO_MCR_ISOLATE_MASK WBGEN2_GEN_MASK(10, 1)
#define MDIO_MCR_ISOLATE_SHIFT 10
#define MDIO_MCR_ISOLATE_W(value) WBGEN2_GEN_WRITE(value, 10, 1)
#define MDIO_MCR_ISOLATE_R(reg) WBGEN2_GEN_READ(reg, 10, 1)
/* definitions for field: Power Down in reg: MDIO Control Register */
#define MDIO_MCR_PDOWN WBGEN2_GEN_MASK(11, 1)
/* definitions for field: Auto-Negotiation Enable in reg: MDIO Control Register */
#define MDIO_MCR_ANENABLE WBGEN2_GEN_MASK(12, 1)
/* definitions for field: Speed Selection (LSB) in reg: MDIO Control Register */
#define MDIO_MCR_SPEED100_MASK WBGEN2_GEN_MASK(13, 1)
#define MDIO_MCR_SPEED100_SHIFT 13
#define MDIO_MCR_SPEED100_W(value) WBGEN2_GEN_WRITE(value, 13, 1)
#define MDIO_MCR_SPEED100_R(reg) WBGEN2_GEN_READ(reg, 13, 1)
/* definitions for field: Loopback in reg: MDIO Control Register */
#define MDIO_MCR_LOOPBACK WBGEN2_GEN_MASK(14, 1)
/* definitions for field: Reset in reg: MDIO Control Register */
#define MDIO_MCR_RESET WBGEN2_GEN_MASK(15, 1)
/* definitions for register: MDIO Status Register */
/* definitions for field: Extended Capability in reg: MDIO Status Register */
#define MDIO_MSR_ERCAP_MASK WBGEN2_GEN_MASK(0, 1)
#define MDIO_MSR_ERCAP_SHIFT 0
#define MDIO_MSR_ERCAP_W(value) WBGEN2_GEN_WRITE(value, 0, 1)
#define MDIO_MSR_ERCAP_R(reg) WBGEN2_GEN_READ(reg, 0, 1)
/* definitions for field: Jabber Detect in reg: MDIO Status Register */
#define MDIO_MSR_JCD_MASK WBGEN2_GEN_MASK(1, 1)
#define MDIO_MSR_JCD_SHIFT 1
#define MDIO_MSR_JCD_W(value) WBGEN2_GEN_WRITE(value, 1, 1)
#define MDIO_MSR_JCD_R(reg) WBGEN2_GEN_READ(reg, 1, 1)
/* definitions for field: Link Status in reg: MDIO Status Register */
#define MDIO_MSR_LSTATUS WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Auto-Negotiation Ability in reg: MDIO Status Register */
#define MDIO_MSR_ANEGCAPABLE_MASK WBGEN2_GEN_MASK(3, 1)
#define MDIO_MSR_ANEGCAPABLE_SHIFT 3
#define MDIO_MSR_ANEGCAPABLE_W(value) WBGEN2_GEN_WRITE(value, 3, 1)
#define MDIO_MSR_ANEGCAPABLE_R(reg) WBGEN2_GEN_READ(reg, 3, 1)
/* definitions for field: Remote Fault in reg: MDIO Status Register */
#define MDIO_MSR_RFAULT WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Auto-Negotiation Complete in reg: MDIO Status Register */
#define MDIO_MSR_ANEGCOMPLETE WBGEN2_GEN_MASK(5, 1)
/* definitions for field: MF Preamble Suppression in reg: MDIO Status Register */
#define MDIO_MSR_MFSUPPRESS_MASK WBGEN2_GEN_MASK(6, 1)
#define MDIO_MSR_MFSUPPRESS_SHIFT 6
#define MDIO_MSR_MFSUPPRESS_W(value) WBGEN2_GEN_WRITE(value, 6, 1)
#define MDIO_MSR_MFSUPPRESS_R(reg) WBGEN2_GEN_READ(reg, 6, 1)
/* definitions for field: Unidirectional Ability in reg: MDIO Status Register */
#define MDIO_MSR_UNIDIRABLE_MASK WBGEN2_GEN_MASK(7, 1)
#define MDIO_MSR_UNIDIRABLE_SHIFT 7
#define MDIO_MSR_UNIDIRABLE_W(value) WBGEN2_GEN_WRITE(value, 7, 1)
#define MDIO_MSR_UNIDIRABLE_R(reg) WBGEN2_GEN_READ(reg, 7, 1)
/* definitions for field: Extended Status Capable in reg: MDIO Status Register */
#define MDIO_MSR_ESTATEN_MASK WBGEN2_GEN_MASK(8, 1)
#define MDIO_MSR_ESTATEN_SHIFT 8
#define MDIO_MSR_ESTATEN_W(value) WBGEN2_GEN_WRITE(value, 8, 1)
#define MDIO_MSR_ESTATEN_R(reg) WBGEN2_GEN_READ(reg, 8, 1)
/* definitions for field: 100BASE-T2 Half Duplex in reg: MDIO Status Register */
#define MDIO_MSR_100HALF2_MASK WBGEN2_GEN_MASK(9, 1)
#define MDIO_MSR_100HALF2_SHIFT 9
#define MDIO_MSR_100HALF2_W(value) WBGEN2_GEN_WRITE(value, 9, 1)
#define MDIO_MSR_100HALF2_R(reg) WBGEN2_GEN_READ(reg, 9, 1)
/* definitions for field: 100BASE-T2 Full Duplex in reg: MDIO Status Register */
#define MDIO_MSR_100FULL2_MASK WBGEN2_GEN_MASK(10, 1)
#define MDIO_MSR_100FULL2_SHIFT 10
#define MDIO_MSR_100FULL2_W(value) WBGEN2_GEN_WRITE(value, 10, 1)
#define MDIO_MSR_100FULL2_R(reg) WBGEN2_GEN_READ(reg, 10, 1)
/* definitions for field: 10 Mbps Half Duplex in reg: MDIO Status Register */
#define MDIO_MSR_10HALF_MASK WBGEN2_GEN_MASK(11, 1)
#define MDIO_MSR_10HALF_SHIFT 11
#define MDIO_MSR_10HALF_W(value) WBGEN2_GEN_WRITE(value, 11, 1)
#define MDIO_MSR_10HALF_R(reg) WBGEN2_GEN_READ(reg, 11, 1)
/* definitions for field: 10 Mbps Full Duplex in reg: MDIO Status Register */
#define MDIO_MSR_10FULL_MASK WBGEN2_GEN_MASK(12, 1)
#define MDIO_MSR_10FULL_SHIFT 12
#define MDIO_MSR_10FULL_W(value) WBGEN2_GEN_WRITE(value, 12, 1)
#define MDIO_MSR_10FULL_R(reg) WBGEN2_GEN_READ(reg, 12, 1)
/* definitions for field: 100BASE-X Half Duplex in reg: MDIO Status Register */
#define MDIO_MSR_100HALF_MASK WBGEN2_GEN_MASK(13, 1)
#define MDIO_MSR_100HALF_SHIFT 13
#define MDIO_MSR_100HALF_W(value) WBGEN2_GEN_WRITE(value, 13, 1)
#define MDIO_MSR_100HALF_R(reg) WBGEN2_GEN_READ(reg, 13, 1)
/* definitions for field: 100BASE-X Full Duplex in reg: MDIO Status Register */
#define MDIO_MSR_100FULL_MASK WBGEN2_GEN_MASK(14, 1)
#define MDIO_MSR_100FULL_SHIFT 14
#define MDIO_MSR_100FULL_W(value) WBGEN2_GEN_WRITE(value, 14, 1)
#define MDIO_MSR_100FULL_R(reg) WBGEN2_GEN_READ(reg, 14, 1)
/* definitions for field: 100BASE-T4 in reg: MDIO Status Register */
#define MDIO_MSR_100BASE4_MASK WBGEN2_GEN_MASK(15, 1)
#define MDIO_MSR_100BASE4_SHIFT 15
#define MDIO_MSR_100BASE4_W(value) WBGEN2_GEN_WRITE(value, 15, 1)
#define MDIO_MSR_100BASE4_R(reg) WBGEN2_GEN_READ(reg, 15, 1)
/* definitions for register: MDIO PHY Identification Register 1 */
/* definitions for field: Organizationally Unique Identifier (bits 7-21) in reg: MDIO PHY Identification Register 1 */
#define MDIO_PHYSID1_OUI_MASK WBGEN2_GEN_MASK(0, 16)
#define MDIO_PHYSID1_OUI_SHIFT 0
#define MDIO_PHYSID1_OUI_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define MDIO_PHYSID1_OUI_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: MDIO PHY Identification Register 2 */
/* definitions for field: Revision Number in reg: MDIO PHY Identification Register 2 */
#define MDIO_PHYSID2_REV_NUM_MASK WBGEN2_GEN_MASK(0, 4)
#define MDIO_PHYSID2_REV_NUM_SHIFT 0
#define MDIO_PHYSID2_REV_NUM_W(value) WBGEN2_GEN_WRITE(value, 0, 4)
#define MDIO_PHYSID2_REV_NUM_R(reg) WBGEN2_GEN_READ(reg, 0, 4)
/* definitions for field: Manufacturer Model Number in reg: MDIO PHY Identification Register 2 */
#define MDIO_PHYSID2_MMNUM_MASK WBGEN2_GEN_MASK(4, 6)
#define MDIO_PHYSID2_MMNUM_SHIFT 4
#define MDIO_PHYSID2_MMNUM_W(value) WBGEN2_GEN_WRITE(value, 4, 6)
#define MDIO_PHYSID2_MMNUM_R(reg) WBGEN2_GEN_READ(reg, 4, 6)
/* definitions for field: Organizationally Unique Identifier (bits 0-5) in reg: MDIO PHY Identification Register 2 */
#define MDIO_PHYSID2_OUI_MASK WBGEN2_GEN_MASK(10, 6)
#define MDIO_PHYSID2_OUI_SHIFT 10
#define MDIO_PHYSID2_OUI_W(value) WBGEN2_GEN_WRITE(value, 10, 6)
#define MDIO_PHYSID2_OUI_R(reg) WBGEN2_GEN_READ(reg, 10, 6)
/* definitions for register: MDIO Auto-Negotiation Advertisement Register */
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_RSVD3_MASK WBGEN2_GEN_MASK(0, 5)
#define MDIO_ADVERTISE_RSVD3_SHIFT 0
#define MDIO_ADVERTISE_RSVD3_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define MDIO_ADVERTISE_RSVD3_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Full Duplex in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_FULL_MASK WBGEN2_GEN_MASK(5, 1)
#define MDIO_ADVERTISE_FULL_SHIFT 5
#define MDIO_ADVERTISE_FULL_W(value) WBGEN2_GEN_WRITE(value, 5, 1)
#define MDIO_ADVERTISE_FULL_R(reg) WBGEN2_GEN_READ(reg, 5, 1)
/* definitions for field: Half Duplex in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_HALF_MASK WBGEN2_GEN_MASK(6, 1)
#define MDIO_ADVERTISE_HALF_SHIFT 6
#define MDIO_ADVERTISE_HALF_W(value) WBGEN2_GEN_WRITE(value, 6, 1)
#define MDIO_ADVERTISE_HALF_R(reg) WBGEN2_GEN_READ(reg, 6, 1)
/* definitions for field: Pause in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_PAUSE_MASK WBGEN2_GEN_MASK(7, 2)
#define MDIO_ADVERTISE_PAUSE_SHIFT 7
#define MDIO_ADVERTISE_PAUSE_W(value) WBGEN2_GEN_WRITE(value, 7, 2)
#define MDIO_ADVERTISE_PAUSE_R(reg) WBGEN2_GEN_READ(reg, 7, 2)
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_RSVD2_MASK WBGEN2_GEN_MASK(9, 3)
#define MDIO_ADVERTISE_RSVD2_SHIFT 9
#define MDIO_ADVERTISE_RSVD2_W(value) WBGEN2_GEN_WRITE(value, 9, 3)
#define MDIO_ADVERTISE_RSVD2_R(reg) WBGEN2_GEN_READ(reg, 9, 3)
/* definitions for field: Remote Fault in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_RFAULT_MASK WBGEN2_GEN_MASK(12, 2)
#define MDIO_ADVERTISE_RFAULT_SHIFT 12
#define MDIO_ADVERTISE_RFAULT_W(value) WBGEN2_GEN_WRITE(value, 12, 2)
#define MDIO_ADVERTISE_RFAULT_R(reg) WBGEN2_GEN_READ(reg, 12, 2)
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_RSVD1_MASK WBGEN2_GEN_MASK(14, 1)
#define MDIO_ADVERTISE_RSVD1_SHIFT 14
#define MDIO_ADVERTISE_RSVD1_W(value) WBGEN2_GEN_WRITE(value, 14, 1)
#define MDIO_ADVERTISE_RSVD1_R(reg) WBGEN2_GEN_READ(reg, 14, 1)
/* definitions for field: Next Page in reg: MDIO Auto-Negotiation Advertisement Register */
#define MDIO_ADVERTISE_NPAGE_MASK WBGEN2_GEN_MASK(15, 1)
#define MDIO_ADVERTISE_NPAGE_SHIFT 15
#define MDIO_ADVERTISE_NPAGE_W(value) WBGEN2_GEN_WRITE(value, 15, 1)
#define MDIO_ADVERTISE_NPAGE_R(reg) WBGEN2_GEN_READ(reg, 15, 1)
/* definitions for register: MDIO Auto-Negotiation Link Partner Ability Register */
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_RSVD3_MASK WBGEN2_GEN_MASK(0, 5)
#define MDIO_LPA_RSVD3_SHIFT 0
#define MDIO_LPA_RSVD3_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define MDIO_LPA_RSVD3_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Full Duplex in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_FULL WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Half Duplex in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_HALF WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Pause in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_PAUSE_MASK WBGEN2_GEN_MASK(7, 2)
#define MDIO_LPA_PAUSE_SHIFT 7
#define MDIO_LPA_PAUSE_W(value) WBGEN2_GEN_WRITE(value, 7, 2)
#define MDIO_LPA_PAUSE_R(reg) WBGEN2_GEN_READ(reg, 7, 2)
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_RSVD2_MASK WBGEN2_GEN_MASK(9, 3)
#define MDIO_LPA_RSVD2_SHIFT 9
#define MDIO_LPA_RSVD2_W(value) WBGEN2_GEN_WRITE(value, 9, 3)
#define MDIO_LPA_RSVD2_R(reg) WBGEN2_GEN_READ(reg, 9, 3)
/* definitions for field: Remote Fault in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_RFAULT_MASK WBGEN2_GEN_MASK(12, 2)
#define MDIO_LPA_RFAULT_SHIFT 12
#define MDIO_LPA_RFAULT_W(value) WBGEN2_GEN_WRITE(value, 12, 2)
#define MDIO_LPA_RFAULT_R(reg) WBGEN2_GEN_READ(reg, 12, 2)
/* definitions for field: Acknowledge in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_LPACK WBGEN2_GEN_MASK(14, 1)
/* definitions for field: Next Page in reg: MDIO Auto-Negotiation Link Partner Ability Register */
#define MDIO_LPA_NPAGE WBGEN2_GEN_MASK(15, 1)
/* definitions for register: MDIO Auto-Negotiation Expansion Register */
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Expansion Register */
#define MDIO_EXPANSION_RSVD1_MASK WBGEN2_GEN_MASK(0, 1)
#define MDIO_EXPANSION_RSVD1_SHIFT 0
#define MDIO_EXPANSION_RSVD1_W(value) WBGEN2_GEN_WRITE(value, 0, 1)
#define MDIO_EXPANSION_RSVD1_R(reg) WBGEN2_GEN_READ(reg, 0, 1)
/* definitions for field: Page Received in reg: MDIO Auto-Negotiation Expansion Register */
#define MDIO_EXPANSION_LWCP_MASK WBGEN2_GEN_MASK(1, 1)
#define MDIO_EXPANSION_LWCP_SHIFT 1
#define MDIO_EXPANSION_LWCP_W(value) WBGEN2_GEN_WRITE(value, 1, 1)
#define MDIO_EXPANSION_LWCP_R(reg) WBGEN2_GEN_READ(reg, 1, 1)
/* definitions for field: Next Page Able in reg: MDIO Auto-Negotiation Expansion Register */
#define MDIO_EXPANSION_ENABLENPAGE_MASK WBGEN2_GEN_MASK(2, 1)
#define MDIO_EXPANSION_ENABLENPAGE_SHIFT 2
#define MDIO_EXPANSION_ENABLENPAGE_W(value) WBGEN2_GEN_WRITE(value, 2, 1)
#define MDIO_EXPANSION_ENABLENPAGE_R(reg) WBGEN2_GEN_READ(reg, 2, 1)
/* definitions for field: Reserved in reg: MDIO Auto-Negotiation Expansion Register */
#define MDIO_EXPANSION_RSVD2_MASK WBGEN2_GEN_MASK(3, 13)
#define MDIO_EXPANSION_RSVD2_SHIFT 3
#define MDIO_EXPANSION_RSVD2_W(value) WBGEN2_GEN_WRITE(value, 3, 13)
#define MDIO_EXPANSION_RSVD2_R(reg) WBGEN2_GEN_READ(reg, 3, 13)
/* definitions for register: MDIO Extended Status Register */
/* definitions for field: Reserved in reg: MDIO Extended Status Register */
#define MDIO_ESTATUS_RSVD1_MASK WBGEN2_GEN_MASK(0, 12)
#define MDIO_ESTATUS_RSVD1_SHIFT 0
#define MDIO_ESTATUS_RSVD1_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define MDIO_ESTATUS_RSVD1_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: 1000Base-T Half Duplex in reg: MDIO Extended Status Register */
#define MDIO_ESTATUS_1000_THALF_MASK WBGEN2_GEN_MASK(12, 1)
#define MDIO_ESTATUS_1000_THALF_SHIFT 12
#define MDIO_ESTATUS_1000_THALF_W(value) WBGEN2_GEN_WRITE(value, 12, 1)
#define MDIO_ESTATUS_1000_THALF_R(reg) WBGEN2_GEN_READ(reg, 12, 1)
/* definitions for field: 1000Base-T Full Duplex in reg: MDIO Extended Status Register */
#define MDIO_ESTATUS_1000_TFULL_MASK WBGEN2_GEN_MASK(13, 1)
#define MDIO_ESTATUS_1000_TFULL_SHIFT 13
#define MDIO_ESTATUS_1000_TFULL_W(value) WBGEN2_GEN_WRITE(value, 13, 1)
#define MDIO_ESTATUS_1000_TFULL_R(reg) WBGEN2_GEN_READ(reg, 13, 1)
/* definitions for field: 1000Base-X Half Duplex in reg: MDIO Extended Status Register */
#define MDIO_ESTATUS_1000_XHALF_MASK WBGEN2_GEN_MASK(14, 1)
#define MDIO_ESTATUS_1000_XHALF_SHIFT 14
#define MDIO_ESTATUS_1000_XHALF_W(value) WBGEN2_GEN_WRITE(value, 14, 1)
#define MDIO_ESTATUS_1000_XHALF_R(reg) WBGEN2_GEN_READ(reg, 14, 1)
/* definitions for field: 1000Base-X Full Duplex in reg: MDIO Extended Status Register */
#define MDIO_ESTATUS_1000_XFULL_MASK WBGEN2_GEN_MASK(15, 1)
#define MDIO_ESTATUS_1000_XFULL_SHIFT 15
#define MDIO_ESTATUS_1000_XFULL_W(value) WBGEN2_GEN_WRITE(value, 15, 1)
#define MDIO_ESTATUS_1000_XFULL_R(reg) WBGEN2_GEN_READ(reg, 15, 1)
/* definitions for register: WhiteRabbit-specific Configuration Register */
/* definitions for field: TX Calibration Pattern in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_TX_CAL WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Calibration Pattern RX Status in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_RX_CAL_STAT WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Reset calibration counter in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_CAL_CRST WBGEN2_GEN_MASK(2, 1)
/* definitions for field: GTP RX Bitslide in reg: WhiteRabbit-specific Configuration Register */
#define MDIO_WR_SPEC_BSLIDE_MASK WBGEN2_GEN_MASK(4, 5)
#define MDIO_WR_SPEC_BSLIDE_SHIFT 4
#define MDIO_WR_SPEC_BSLIDE_W(value) WBGEN2_GEN_WRITE(value, 4, 5)
#define MDIO_WR_SPEC_BSLIDE_R(reg) WBGEN2_GEN_READ(reg, 4, 5)
PACKED struct MDIO_WB {
/* [0x0]: REG MDIO Control Register */
uint32_t MCR;
/* [0x4]: REG MDIO Status Register */
uint32_t MSR;
/* [0x8]: REG MDIO PHY Identification Register 1 */
uint32_t PHYSID1;
/* [0xc]: REG MDIO PHY Identification Register 2 */
uint32_t PHYSID2;
/* [0x10]: REG MDIO Auto-Negotiation Advertisement Register */
uint32_t ADVERTISE;
/* [0x14]: REG MDIO Auto-Negotiation Link Partner Ability Register */
uint32_t LPA;
/* [0x18]: REG MDIO Auto-Negotiation Expansion Register */
uint32_t EXPANSION;
/* padding to: 15 words */
uint32_t __padding_0[8];
/* [0x3c]: REG MDIO Extended Status Register */
uint32_t ESTATUS;
/* [0x40]: REG WhiteRabbit-specific Configuration Register */
uint32_t WR_SPEC;
};
#endif
kernel/wbgen-regs/endpoint-mdio.wb 0 → 100644
View file @ dc7a4c3c
-- -*- Mode: LUA; tab-width: 2 -*-
-------------------------------------------------------------------------------
-- Title : 802.3 PCS Register Block (slave)
-- Project : White Rabbit MAC/Endpoint
-------------------------------------------------------------------------------
-- File : pcs_regs.wb
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-10-18
-------------------------------------------------------------------------------
-- Description: Standard PCS register block + WR-specific PCS fields:
-- RX bitslide and calibration pattern control.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1l.html
--
-------------------------------------------------------------------------------
peripheral {
name = "WR Endpoint 1000base-X TBI PCS register block";
hdl_entity = "ep_pcs_tbi_mdio_wb";
prefix = "MDIO";
reg {
name = "MDIO Control Register";
prefix = "MCR";
field {
name = "Reserved";
description = "Always return 0s, writes ignored.";
prefix = "RESV";
type = CONSTANT;
size = 5;
value = 0;
};
field {
name = "Unidirectional Enable";
description = "1 = Enable transmit regardless of whether a valid link has been established\
0 = Normal operation";
prefix = "uni_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Speed Selection (MSB)";
description = "Always 1, indicating (together with bit 13) a fixed speed of 1000 Mbps";
prefix = "SPEED1000";
type = CONSTANT;
size = 1;
value = 1;
};
field {
name = "Collision Test";
description = "Always equal to 0, since collision detection is not supported";
prefix = "ctst";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "Duplex Mode";
description = "Always equal to 1 to indicate Full-Duplex operation";
prefix = "fulldplx";
type = CONSTANT;
size = 1;
value = 1;
};
field {
name = "Restart Auto-Negotiation";
description = "write 1 = restart Auto-Negotiation process\
write 0 = no effect";
prefix = "anrestart";
type = MONOSTABLE;
};
field {
name = "Isolate";
description = "GMII Electrical isolation enable. Ignored since the PCS doesn't use GMII";
prefix = "isolate";
size = 1;
type = CONSTANT;
value = 0;
};
field {
name = "Power Down";
description = "1 = Power down \
0 = Normal operation \
This bit controls directly the PHY Enable pin";
prefix = "pdown";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Auto-Negotiation Enable";
description = "1 = Enable Auto-Negotiation process \
0 = Disable Auto-Negotiation process";
prefix = "anenable";
align = 12;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Speed Selection (LSB)";
description = "Always 0, indicating (together with bit 6) a fixed speed of 1000 Mbps";
align = 13;
prefix = "SPEED100";
size = 1;
type = CONSTANT;
value = 0;
};
field {
name = "Loopback";
description = "1 = enable loopback mode \
0 = disable loopback mode \
With the TBI version, loopback bit is connected to PHY loopback enable pin. When set to 1, indicates to the external PHY to enter loopback mode";
prefix = "loopback";
align = 14;
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reset";
description = "write 1 = triggers reset of the PCS core\
write 0 = no effect";
align = 15;
prefix = "reset";
type = MONOSTABLE;
};
};
reg {
name = "MDIO Status Register";
prefix = "MSR";
-- options = READ_STROBE;
field {
name = "Extended Capability";
description = "Always 0, since extended register set is not supported";
prefix = "ERCAP";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "Jabber Detect";
description = "Always 0, since Jabber Detect is not supported";
prefix = "JCD";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "Link Status";
description = "1 = Link is up\
0 = Link is down (or has been down)\
Latches '0' if Link Status goes down. Clears to current Link Status on read.";
prefix = "LSTATUS";
type = BIT;
access_bus=READ_ONLY;
access_dev=WRITE_ONLY;
ack_read="lstat_read_notify_o";
};
field {
name = "Auto-Negotiation Ability";
description = "Always 1, to indicate the support for Auto-Negotiation.";
prefix = "ANEGCAPABLE";
type = CONSTANT;
size = 1;
value = 1;
};
field {
name = "Remote Fault";
description = "1 = Remote fault condition detected\
0 = No remote fault condition detected\
The bit clears itself after being read by the host.";
prefix = "RFAULT";
type = BIT;
access_bus=READ_ONLY;
access_dev=WRITE_ONLY;
};
field {
name = "Auto-Negotiation Complete";
description = "1 = Auto-Negotiation process completed\
0 = Auto-Negotiation process not completed";
prefix = "anegcomplete";
type = BIT;
access_bus=READ_ONLY;
access_dev=WRITE_ONLY;
};
field {
name = "MF Preamble Suppression";
description = "Always 0, feature not supported. ";
prefix = "mfsuppress";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "Unidirectional Ability";
description = "Always 1, as the Unidirectional mode is supported. ";
prefix = "unidirable";
type = CONSTANT;
size = 1;
value = 1;
};
field {
name = "Extended Status Capable";
description = "Always 1, indicating the presence of the Extended Status Register";
prefix = "estaten";
type = CONSTANT;
size = 1;
value = 1;
};
field {
name = "100BASE-T2 Half Duplex";
description = "Always 0 (unsupported medium)";
prefix = "100half2";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "100BASE-T2 Full Duplex";
description = "Always 0 (unsupported medium)";
prefix = "100full2";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "10 Mbps Half Duplex";
description = "Always 0 (unsupported medium)";
prefix = "10half";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "10 Mbps Full Duplex";
description = "Always 0 (unsupported medium)";
prefix = "10full";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "100BASE-X Half Duplex";
description = "Always 0 (unsupported medium)";
prefix = "100half";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "100BASE-X Full Duplex";
description = "Always 0 (unsupported medium)";
prefix = "100full";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "100BASE-T4";
description = "Always 0 (unsupported medium)";
prefix = "100base4";
type = CONSTANT;
size = 1;
value = 0;
};
};
reg {
name = "MDIO PHY Identification Register 1";
prefix = "PHYSID1";
field {
name = " Organizationally Unique Identifier (bits 7-21)";
description = "Always 0.";
prefix = "OUI";
type = CONSTANT;
size = 16;
value = 0;
};
};
reg {
name = "MDIO PHY Identification Register 2";
prefix = "PHYSID2";
field {
name = "Revision Number";
description = "Always 0.";
prefix = "REV_NUM";
type = CONSTANT;
size = 4;
value = 0;
};
field {
name = "Manufacturer Model Number";
description = "Always 0.";
prefix = "MMNUM";
type = CONSTANT;
size = 6;
value = 0;
};
field {
name = "Organizationally Unique Identifier (bits 0-5)";
description = "Always 0.";
prefix = "OUI";
type = CONSTANT;
size = 6;
value = 0;
};
};
reg {
name = "MDIO Auto-Negotiation Advertisement Register";
prefix = "ADVERTISE";
field {
name = "Reserved";
description = "Always 0.";
prefix = "RSVD3";
type = CONSTANT;
size = 5;
value = 0;
};
field {
name = "Full Duplex";
description = "Always 1, since Full Duplex Mode is the only supported mode.";
prefix = "FULL";
type = CONSTANT;
size = 1;
value = 1;
};
field {
name = "Half Duplex";
description = "Always 0, since Half Duplex Mode is not supported.";
prefix = "HALF";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "Pause";
description = "00 = No PAUSE\
01 = Symmetric PAUSE \
10 = Asymmetric PAUSE towards link partner\
11 = Both Symmetric PAUSE and Asymmetric PAUSE towards link partner";
prefix = "PAUSE";
type = SLV;
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Always 0.";
prefix = "RSVD2";
type = CONSTANT;
size = 3;
value = 0;
};
field {
name = "Remote Fault";
description = "00 = No Error \
01 = Offline \
10 = Link Failure \
11 = Auto-Negotiation Error";
prefix = "RFAULT";
type = SLV;
size = 2;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Reserved";
description = "Always 0.";
prefix = "RSVD1";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "Next Page";
description = "Always 0, since Next Page feature is not supported";
prefix = "NPAGE";
type = CONSTANT;
size = 1;
value = 0;
};
};
reg {
name = "MDIO Auto-Negotiation Link Partner Ability Register";
prefix = "LPA";
field {
name = "Reserved";
description = "Always 0.";
prefix = "RSVD3";
type = CONSTANT;
size = 5;
value = 0;
};
field {
name = "Full Duplex";
description = "1 = Remote partner supports Full Duplex operation\
0 = It doesn't";
prefix = "FULL";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Half Duplex";
description = "1 = Remote partner supports Half Duplex operation\
0 = It doesn't";
prefix = "HALF";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Pause";
description = "00 = No PAUSE\
01 = Symmetric PAUSE \
10 = Asymmetric PAUSE towards link partner\
11 = Both Symmetric PAUSE and Asymmetric PAUSE towards link partner";
prefix = "PAUSE";
type = SLV;
size = 2;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Reserved";
description = "Always 0.";
prefix = "RSVD2";
type = CONSTANT;
size = 3;
value = 0;
};
field {
name = "Remote Fault";
description = "00 = No Error \
01 = Offline \
10 = Link Failure \
11 = Auto-Negotiation Error";
prefix = "RFAULT";
type = SLV;
size = 2;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Acknowledge";
description = "Used by Auto-Negotiation function to indicate reception of a link partner's base or next page.";
prefix = "LPACK";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Next Page";
description = "1 = Next Page functionality is supported\
0 = It isn't";
prefix = "NPAGE";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "MDIO Auto-Negotiation Expansion Register";
prefix = "EXPANSION";
field {
name = "Reserved";
description = "Always 0.";
prefix = "RSVD1";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "Page Received";
description = "Always 0, since we don't support the Next Page function";
prefix = "LWCP";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "Next Page Able";
description = "Always 0, since we don't support the Next Page function";
prefix = "ENABLENPAGE";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "Reserved";
description = "Always 0.";
prefix = "RSVD2";
type = CONSTANT;
size = 13;
value = 0;
};
};
reg {
name = "MDIO Extended Status Register";
prefix = "ESTATUS";
align=15;
field {
name = "Reserved";
description = "Always 0.";
prefix = "RSVD1";
type = CONSTANT;
size = 12;
value = 0;
};
field {
name = "1000Base-T Half Duplex";
description = "Always 0, since this mode is not supported.";
prefix = "1000_THALF";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "1000Base-T Full Duplex";
description = "Always 0, since this mode is not supported.";
prefix = "1000_TFULL";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "1000Base-X Half Duplex";
description = "Always 0, since this mode is not supported.";
prefix = "1000_XHALF";
type = CONSTANT;
size = 1;
value = 0;
};
field {
name = "1000Base-X Full Duplex";
description = "Always 1, indicating the support for 1000Base-X Full Duplex mode.";
prefix = "1000_XFULL";
type = CONSTANT;
size = 1;
value = 1;
};
};
reg {
name = "WhiteRabbit-specific Configuration Register";
prefix = "WR_SPEC";
field {
name = "TX Calibration Pattern";
description = "Controls the transmission of WR PHY calibration pattern. \
1 = PCS is sending calibration pattern\
0 = Normal PCS operation";
prefix = "TX_CAL";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "tx_clk_i";
};
field {
name = "Calibration Pattern RX Status";
description = "1 = Valid calibration pattern is being received\
0 = no calibration pattern detected by the receiver";
prefix = "RX_CAL_STAT";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "rx_clk_i";
};
field {
name = "Reset calibration counter";
prefix = "CAL_CRST";
description = "1: resets the calibration pattern valid counter. \
0: no effect";
type = MONOSTABLE;
clock = "rx_clk_i";
};
field {
name = "GTP RX Bitslide";
prefix = "BSLIDE";
description = "Current receive path bit slide (valid only for Xilinx GTP/GTX versions)";
type = SLV;
size = 5;
align = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "rx_clk_i";
};
};
};
kernel/wbgen-regs/endpoint-regs.h 0 → 100644
View file @ dc7a4c3c
/*
Register definitions for slave core: WR switch endpoint controller
* File : endpoint-regs.h
* Author : auto-generated by wbgen2 from endpoint-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE endpoint-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_ENDPOINT
#define __WBGEN2_REGDEFS_ENDPOINT
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Endpoint Control Register */
/* definitions for field: Port identifier in reg: Endpoint Control Register */
#define EP_ECR_PORTID_MASK WBGEN2_GEN_MASK(0, 5)
#define EP_ECR_PORTID_SHIFT 0
#define EP_ECR_PORTID_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define EP_ECR_PORTID_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Reset event counters in reg: Endpoint Control Register */
#define EP_ECR_RST_CNT WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Transmit path enable in reg: Endpoint Control Register */
#define EP_ECR_TX_EN WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Receive path enable in reg: Endpoint Control Register */
#define EP_ECR_RX_EN WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Feature present: VLAN tagging in reg: Endpoint Control Register */
#define EP_ECR_FEAT_VLAN WBGEN2_GEN_MASK(24, 1)
/* definitions for field: Feature present: DDMTD phase measurement in reg: Endpoint Control Register */
#define EP_ECR_FEAT_DMTD WBGEN2_GEN_MASK(25, 1)
/* definitions for field: Feature present: IEEE1588 timestamper in reg: Endpoint Control Register */
#define EP_ECR_FEAT_PTP WBGEN2_GEN_MASK(26, 1)
/* definitions for field: Feature present: DPI packet classifier in reg: Endpoint Control Register */
#define EP_ECR_FEAT_DPI WBGEN2_GEN_MASK(27, 1)
/* definitions for register: Timestamping Control Register */
/* definitions for field: Transmit timestamping enable in reg: Timestamping Control Register */
#define EP_TSCR_EN_TXTS WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Receive timestamping enable in reg: Timestamping Control Register */
#define EP_TSCR_EN_RXTS WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamping counter synchronization start in reg: Timestamping Control Register */
#define EP_TSCR_CS_START WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Timestamping counter synchronization done in reg: Timestamping Control Register */
#define EP_TSCR_CS_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for register: RX Deframer Control Register */
/* definitions for field: RX accept runts in reg: RX Deframer Control Register */
#define EP_RFCR_A_RUNT WBGEN2_GEN_MASK(0, 1)
/* definitions for field: RX accept giants in reg: RX Deframer Control Register */
#define EP_RFCR_A_GIANT WBGEN2_GEN_MASK(1, 1)
/* definitions for field: RX accept HP in reg: RX Deframer Control Register */
#define EP_RFCR_A_HP WBGEN2_GEN_MASK(2, 1)
/* definitions for field: RX keep CRC in reg: RX Deframer Control Register */
#define EP_RFCR_KEEP_CRC WBGEN2_GEN_MASK(3, 1)
/* definitions for field: RX Fiter HP Priorities in reg: RX Deframer Control Register */
#define EP_RFCR_HPAP_MASK WBGEN2_GEN_MASK(4, 8)
#define EP_RFCR_HPAP_SHIFT 4
#define EP_RFCR_HPAP_W(value) WBGEN2_GEN_WRITE(value, 4, 8)
#define EP_RFCR_HPAP_R(reg) WBGEN2_GEN_READ(reg, 4, 8)
/* definitions for field: Maximum receive unit (MRU) in reg: RX Deframer Control Register */
#define EP_RFCR_MRU_MASK WBGEN2_GEN_MASK(12, 14)
#define EP_RFCR_MRU_SHIFT 12
#define EP_RFCR_MRU_W(value) WBGEN2_GEN_WRITE(value, 12, 14)
#define EP_RFCR_MRU_R(reg) WBGEN2_GEN_READ(reg, 12, 14)
/* definitions for register: VLAN control register 0 */
/* definitions for field: RX 802.1q port mode in reg: VLAN control register 0 */
#define EP_VCR0_QMODE_MASK WBGEN2_GEN_MASK(0, 2)
#define EP_VCR0_QMODE_SHIFT 0
#define EP_VCR0_QMODE_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define EP_VCR0_QMODE_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Force 802.1q priority in reg: VLAN control register 0 */
#define EP_VCR0_FIX_PRIO WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Port-assigned 802.1q priority in reg: VLAN control register 0 */
#define EP_VCR0_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define EP_VCR0_PRIO_VAL_SHIFT 4
#define EP_VCR0_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define EP_VCR0_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Port-assigned VID in reg: VLAN control register 0 */
#define EP_VCR0_PVID_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_VCR0_PVID_SHIFT 16
#define EP_VCR0_PVID_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_VCR0_PVID_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: VLAN Control Register 1 */
/* definitions for field: Egress untagged set bitmap VID in reg: VLAN Control Register 1 */
#define EP_VCR1_VID_MASK WBGEN2_GEN_MASK(0, 12)
#define EP_VCR1_VID_SHIFT 0
#define EP_VCR1_VID_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define EP_VCR1_VID_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Egress untagged set bitmap value in reg: VLAN Control Register 1 */
#define EP_VCR1_VALUE_MASK WBGEN2_GEN_MASK(12, 1)
#define EP_VCR1_VALUE_SHIFT 12
#define EP_VCR1_VALUE_W(value) WBGEN2_GEN_WRITE(value, 12, 1)
#define EP_VCR1_VALUE_R(reg) WBGEN2_GEN_READ(reg, 12, 1)
/* definitions for register: Packet Filter Control Register 0 */
/* definitions for field: Microcode Memory Address in reg: Packet Filter Control Register 0 */
#define EP_PFCR0_MM_ADDR_MASK WBGEN2_GEN_MASK(0, 6)
#define EP_PFCR0_MM_ADDR_SHIFT 0
#define EP_PFCR0_MM_ADDR_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define EP_PFCR0_MM_ADDR_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for field: Microcode Memory Write Enable in reg: Packet Filter Control Register 0 */
#define EP_PFCR0_MM_WRITE_MASK WBGEN2_GEN_MASK(6, 1)
#define EP_PFCR0_MM_WRITE_SHIFT 6
#define EP_PFCR0_MM_WRITE_W(value) WBGEN2_GEN_WRITE(value, 6, 1)
#define EP_PFCR0_MM_WRITE_R(reg) WBGEN2_GEN_READ(reg, 6, 1)
/* definitions for field: Packet Filter Enable in reg: Packet Filter Control Register 0 */
#define EP_PFCR0_ENABLE WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Microcode Memory Data (24 MSBs) in reg: Packet Filter Control Register 0 */
#define EP_PFCR0_MM_DATA_MSB_MASK WBGEN2_GEN_MASK(8, 24)
#define EP_PFCR0_MM_DATA_MSB_SHIFT 8
#define EP_PFCR0_MM_DATA_MSB_W(value) WBGEN2_GEN_WRITE(value, 8, 24)
#define EP_PFCR0_MM_DATA_MSB_R(reg) WBGEN2_GEN_READ(reg, 8, 24)
/* definitions for register: Packet Filter Control Register 1 */
/* definitions for field: Microcode Memory Data (12 LSBs) in reg: Packet Filter Control Register 1 */
#define EP_PFCR1_MM_DATA_LSB_MASK WBGEN2_GEN_MASK(0, 12)
#define EP_PFCR1_MM_DATA_LSB_SHIFT 0
#define EP_PFCR1_MM_DATA_LSB_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define EP_PFCR1_MM_DATA_LSB_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for register: Traffic Class Assignment Register */
/* definitions for field: 802.1Q priority tag to Traffic Class map in reg: Traffic Class Assignment Register */
#define EP_TCAR_PCP_MAP_MASK WBGEN2_GEN_MASK(0, 24)
#define EP_TCAR_PCP_MAP_SHIFT 0
#define EP_TCAR_PCP_MAP_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define EP_TCAR_PCP_MAP_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for register: Flow Control Register */
/* definitions for field: RX Pause enable in reg: Flow Control Register */
#define EP_FCR_RXPAUSE WBGEN2_GEN_MASK(0, 1)
/* definitions for field: TX Pause enable in reg: Flow Control Register */
#define EP_FCR_TXPAUSE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: TX pause threshold in reg: Flow Control Register */
#define EP_FCR_TX_THR_MASK WBGEN2_GEN_MASK(8, 8)
#define EP_FCR_TX_THR_SHIFT 8
#define EP_FCR_TX_THR_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define EP_FCR_TX_THR_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for field: TX pause quanta in reg: Flow Control Register */
#define EP_FCR_TX_QUANTA_MASK WBGEN2_GEN_MASK(16, 16)
#define EP_FCR_TX_QUANTA_SHIFT 16
#define EP_FCR_TX_QUANTA_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define EP_FCR_TX_QUANTA_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Endpoint MAC address high part register */
/* definitions for register: Endpoint MAC address low part register */
/* definitions for register: MDIO Control Register */
/* definitions for field: MDIO Register Value in reg: MDIO Control Register */
#define EP_MDIO_CR_DATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_CR_DATA_SHIFT 0
#define EP_MDIO_CR_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_CR_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO Register Address in reg: MDIO Control Register */
#define EP_MDIO_CR_ADDR_MASK WBGEN2_GEN_MASK(16, 8)
#define EP_MDIO_CR_ADDR_SHIFT 16
#define EP_MDIO_CR_ADDR_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define EP_MDIO_CR_ADDR_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for field: MDIO Read/Write select in reg: MDIO Control Register */
#define EP_MDIO_CR_RW WBGEN2_GEN_MASK(31, 1)
/* definitions for register: MDIO Address/Status Register */
/* definitions for field: MDIO Read Value in reg: MDIO Address/Status Register */
#define EP_MDIO_ASR_RDATA_MASK WBGEN2_GEN_MASK(0, 16)
#define EP_MDIO_ASR_RDATA_SHIFT 0
#define EP_MDIO_ASR_RDATA_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define EP_MDIO_ASR_RDATA_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: MDIO PHY Address in reg: MDIO Address/Status Register */
#define EP_MDIO_ASR_PHYAD_MASK WBGEN2_GEN_MASK(16, 8)
#define EP_MDIO_ASR_PHYAD_SHIFT 16
#define EP_MDIO_ASR_PHYAD_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define EP_MDIO_ASR_PHYAD_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for field: MDIO Ready in reg: MDIO Address/Status Register */
#define EP_MDIO_ASR_READY WBGEN2_GEN_MASK(31, 1)
/* definitions for register: Identification register */
/* definitions for register: Debug/Status register */
/* definitions for field: Link status in reg: Debug/Status register */
#define EP_DSR_LSTATUS WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Link activity in reg: Debug/Status register */
#define EP_DSR_LACT WBGEN2_GEN_MASK(1, 1)
/* definitions for register: DMTD Control Register */
/* definitions for field: DMTD Phase measurement enable in reg: DMTD Control Register */
#define EP_DMCR_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMTD averaging samples in reg: DMTD Control Register */
#define EP_DMCR_N_AVG_MASK WBGEN2_GEN_MASK(16, 12)
#define EP_DMCR_N_AVG_SHIFT 16
#define EP_DMCR_N_AVG_W(value) WBGEN2_GEN_WRITE(value, 16, 12)
#define EP_DMCR_N_AVG_R(reg) WBGEN2_GEN_READ(reg, 16, 12)
/* definitions for register: DMTD Status register */
/* definitions for field: DMTD Phase shift value in reg: DMTD Status register */
#define EP_DMSR_PS_VAL_MASK WBGEN2_GEN_MASK(0, 24)
#define EP_DMSR_PS_VAL_SHIFT 0
#define EP_DMSR_PS_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define EP_DMSR_PS_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: DMTD Phase shift value ready in reg: DMTD Status register */
#define EP_DMSR_PS_RDY WBGEN2_GEN_MASK(24, 1)
/* definitions for RAM: Event counters memory */
#define EP_RMON_RAM_BASE 0x00000080 /* base address */
#define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */
#define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
PACKED struct EP_WB {
/* [0x0]: REG Endpoint Control Register */
uint32_t ECR;
/* [0x4]: REG Timestamping Control Register */
uint32_t TSCR;
/* [0x8]: REG RX Deframer Control Register */
uint32_t RFCR;
/* [0xc]: REG VLAN control register 0 */
uint32_t VCR0;
/* [0x10]: REG VLAN Control Register 1 */
uint32_t VCR1;
/* [0x14]: REG Packet Filter Control Register 0 */
uint32_t PFCR0;
/* [0x18]: REG Packet Filter Control Register 1 */
uint32_t PFCR1;
/* [0x1c]: REG Traffic Class Assignment Register */
uint32_t TCAR;
/* [0x20]: REG Flow Control Register */
uint32_t FCR;
/* [0x24]: REG Endpoint MAC address high part register */
uint32_t MACH;
/* [0x28]: REG Endpoint MAC address low part register */
uint32_t MACL;
/* [0x2c]: REG MDIO Control Register */
uint32_t MDIO_CR;
/* [0x30]: REG MDIO Address/Status Register */
uint32_t MDIO_ASR;
/* [0x34]: REG Identification register */
uint32_t IDCODE;
/* [0x38]: REG Debug/Status register */
uint32_t DSR;
/* [0x3c]: REG DMTD Control Register */
uint32_t DMCR;
/* [0x40]: REG DMTD Status register */
uint32_t DMSR;
/* padding to: 32 words */
uint32_t __padding_0[15];
/* [0x80 - 0xff]: RAM Event counters memory, 32 32-bit words, 32-bit aligned, word-addressable */
uint32_t RMON_RAM [32];
};
#endif
kernel/wbgen-regs/endpoint-regs.wb 0 → 100644
View file @ dc7a4c3c
-- -*- Mode: LUA; tab-width: 2 -*-
-------------------------------------------------------------------------------
-- Title : Wishbone Register Block (slave)
-- Project : White Rabbit MAC/Endpoint
-------------------------------------------------------------------------------
-- File : ep_wishbone_controller.wb
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-10-18
-------------------------------------------------------------------------------
-- Description: Description of all non-PCS endpoint control registers
-- for wbgen2 Wishbone slave core generator.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1l.html
--
-------------------------------------------------------------------------------
peripheral {
name = "WR switch endpoint controller";
description = "EP controller";
hdl_entity = "ep_wishbone_controller";
prefix = "ep";
-- ECR
reg {
name = "Endpoint Control Register";
prefix = "ECR";
description = "General endpoint control register";
field {
name = "Port identifier";
description = "Unique port identifier which will be embedded into OOB with the timestamp value";
prefix = "PORTID";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 5;
};
field {
name = "Reset event counters";
description = "write 1: resets all event counters\n0: no effect";
prefix = "rst_cnt";
type = MONOSTABLE;
};
field {
name = "Transmit path enable";
description = "1: TX path is enabled\
0: TX path is disabled";
prefix = "TX_EN";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Receive path enable";
prefix = "RX_en";
description = "1: RX path is enabled\
0: RX path is disabled";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Feature present: VLAN tagging";
description = "1: this implementation of WR Endpoint supports VLAN processing \
(tagging/untagging). VCR register can be used to control the \
VLAN functionality \
0: no VLAN support compiled";
prefix = "FEAT_VLAN";
align = 24;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Feature present: DDMTD phase measurement";
description = "1: this implementation of WR Endpoint can do fine phase measurements \
using a DDMTD phase detector\
0: no phase measurement support compiled";
prefix = "FEAT_DMTD";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Feature present: IEEE1588 timestamper";
description = "1: this implementation of WR Endpoint can timestamp packets\
0: no timestamping compiled";
prefix = "FEAT_PTP";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Feature present: DPI packet classifier";
description = "1: this implementation of WR Endpoint includes Deep Packet Inspection packet classifier/filter\
0: no DPI compiled";
prefix = "FEAT_DPI";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Timestamping Control Register";
description = "Register controlling timestamping features of the endpoint";
prefix = "TSCR";
field {
name = "Transmit timestamping enable";
description = "1: enables TX timestamping. Endpoints passes timestamps to shared TX timestamping unit\
0: disables TX timestamping";
prefix = "EN_TXTS";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Receive timestamping enable";
description = "1: enables RX timestamping. RX timestamps are embedded into OOB field on the fabric interface. Must be enabled if used in a multi-port configuration (e.g. in a switch)\
0: disables RX timestamping";
prefix = "EN_RXTS";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "Timestamping counter synchronization start";
prefix = "CS_START";
description = "write 1: starts synchronizing the local PPS counter used for timestamping TX/RX packets with an external pulse provided on pps_i input.\
After synchronization, the CS_DONE flag will be set to 1. The counter value equals to 0 when PPS line is high.\
write 0: no effect";
type = MONOSTABLE;
clock = "tx_clk_i";
};
field {
name = "Timestamping counter synchronization done";
prefix = "CS_DONE";
description = "1: the counter synchronization procedure is done. \
0: the counter synchronization procedure is pending";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "tx_clk_i";
};
};
reg {
name = "RX Deframer Control Register";
prefix = "RFCR";
field {
name = "RX accept runts";
description = "1: endpoint accepts 'runt' frames (shorter than 64 bytes)\
0: 'runt' frames are dropped";
prefix = "A_RUNT";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "RX accept giants";
description = "1: endpoint accepts 'giant' frames (longer than 1516/1522 bytes)\
0: 'giant' frames are dropped";
prefix = "A_GIANT";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "RX accept HP";
description = "1: endpoint accepts HP frames\
0: HP frames are dropped";
prefix = "A_HP";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "RX keep CRC";
description = "1: endpoint keeps FCS fields on the fabric side\
0: FCS fields are stripped";
prefix = "KEEP_CRC";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "RX Fiter HP Priorities";
prefix = "HPAP";
description = "Map of 802.1q PCP values which qualify the incoming frame as HP. Each bit corresponds to one PCP value (bit 7: PCP == 7, bit 0: PCP == 0).";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Maximum receive unit (MRU)";
description = "Maximum size of a frame which is considered valid (in bytes)";
prefix = "MRU";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 14;
};
};
reg {
name = "VLAN control register 0";
prefix = "VCR0";
field {
name = "RX 802.1q port mode";
description = "00: ACCESS port - tags untagged received packets with VID from RX_VID field. Drops all tagged packets not belonging to RX_VID VLAN\
01: TRUNK port - passes only tagged VLAN packets. Drops all untagged packets.\
11: unqualified port - passes all traffic regardless of VLAN configuration";
type = SLV;
size = 2;
align = 2;
prefix = "Qmode";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Force 802.1q priority";
description = "1: ignores the 802.1x priority (if 802.1q header is present) and sets it to fixed value\
0: uses priority from 802.1q header";
prefix = "FIX_PRIO";
type = BIT;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Port-assigned 802.1q priority";
description = "Packet priority value for retagging. When FIX_PRIO is 1, the endpoint uses this value as the packet priority. Otherwise, priority value is taken from 802.1q header if it's present. If there is no 802.1q header, the priority is assumed to be PRIO_VAL.";
prefix = "PRIO_VAL";
type = SLV;
size = 3;
align = 4;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "Port-assigned VID";
description = "VLAN id value for tagging incoming packets if the port is in ACCESS mode. For TRUNK/unqualified the value of VID is ignored.";
prefix = "PVID";
type = SLV;
align = 16;
size = 12;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "VLAN Control Register 1";
description = "Controls the access to the egress VLAN untagged set.\
Each write can enable (VALUE=1) / disable (VALUE=0) untagging frames\
with given VID";
prefix = "VCR1";
field {
name = "Egress untagged set bitmap VID";
description = "write: the VID to be tagged/untagged\
read: undefined";
prefix = "VID";
type = PASS_THROUGH;
size = 12;
};
field {
name = "Egress untagged set bitmap value";
description = "write 1: frames with matching VID are untagged\
write 0: frames with matching VID are not modified\
read: undefined";
prefix = "VALUE";
type = PASS_THROUGH;
size = 1;
};
};
reg {
name = "Packet Filter Control Register 0";
description = "Controls the microcode memory access of the Packet Filter Unit. \
See the Endpoint documentation for more details";
prefix = "PFCR0";
field {
name = "Microcode Memory Address";
prefix = "MM_ADDR";
size = 6;
type = PASS_THROUGH;
};
field {
size = 1;
name = "Microcode Memory Write Enable";
prefix = "MM_WRITE";
type = PASS_THROUGH;
};
field {
type = BIT;
name = "Packet Filter Enable";
prefix = "ENABLE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
size = 24;
name = "Microcode Memory Data (24 MSBs)";
prefix = "MM_DATA_MSB";
type = PASS_THROUGH;
};
};
reg {
name = "Packet Filter Control Register 1";
description = "Controls the microcode memory access of the Packet Filter Unit. \
See the Endpoint documentation for more details";
prefix= "PFCR1";
field{
size = 12;
name = "Microcode Memory Data (12 LSBs)";
prefix = "MM_DATA_LSB";
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Traffic Class Assignment Register";
description = "Controls the mapping of VLAN priority fields into Swcore's traffic classes.. See Endpoint's documentation for more details.";
prefix = "TCAR";
field {
name = "802.1Q priority tag to Traffic Class map";
prefix = "PCP_MAP";
description = "Controls the mapping of PCP into Traffic Classes. The mapping algorithm is: TC = PCP_MAP[PCP * 3 + 2 : PCP * 3]; ";
size = 24;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Flow Control Register";
description = "";
prefix = "FCR";
field {
name = "RX Pause enable";
description = "1: enable reception of pause frames and TX path throttling \
0: disable reception of pause frames";
prefix = "RXPAUSE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "TX Pause enable";
description = "1: enable transmission of pause frames and RX path throttling \
0: disable transmission of pause frames";
prefix = "TXPAUSE";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = BIT;
};
field {
name = "TX pause threshold";
description = "Defines the percentage of space occupied in the RX buffer which triggers the transmission of a PAUSE frame. 0 = empty buffer, 255 = full buffer";
prefix = "TX_THR";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 8;
align = 8;
};
field {
name = "TX pause quanta";
description = "Defines the quanta value carried bypause frames sent by the Endpoint";
prefix = "TX_QUANTA";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
type = SLV;
size = 16;
align = 16;
};
};
reg {
name = "Endpoint MAC address high part register";
prefix = "MACH";
description = "Register containing bits [47:32] of the endpoint's MAC address";
field {
name = "MAC Address";
description = "MAC Address bits [47:32]";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Endpoint MAC address low part register";
description = "Register containing bits [31:0] of the endpoint's MAC address";
prefix = "MACL";
field {
name = "MAC Address";
description = "MAC Address bits [31:0]";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "MDIO Control Register";
description = "Register controlling the read/write operations on the MDIO PHY/PCS interface. Writing to this register clears the READY bit in the MDIO Status Register";
prefix = "MDIO_CR";
field {
name = "MDIO Register Value";
description = "Data word to be written to the MDIO";
prefix = "DATA";
type = PASS_THROUGH;
size = 16;
};
field {
name = "MDIO Register Address";
description = "Address of the MDIO register to be read/written";
prefix = "ADDR";
type = SLV;
size = 8;
};
field {
name = "MDIO Read/Write select";
description = "1 = Performs a write to MDIO register at address ADDR with value DATA\
0 = Reads the value of MDIO register at address ADDR";
prefix = "RW";
align=31;
type = BIT;
};
};
reg {
name = "MDIO Address/Status Register";
description = "Register with the current status of the MDIO interface";
prefix = "MDIO_ASR";
field {
name = "MDIO Read Value";
description = "The value of the recently read MDIO register.";
prefix = "RDATA";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "MDIO PHY Address";
description = "Address of the PHY on the MDIO bus";
prefix = "PHYAD";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "MDIO Ready";
description = "1 = MDIO read/write operation is complete (for read operations, that means that RDATA contains a valid value)\
0 = MDIO operation in progress";
prefix = "READY";
align=31;
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Identification register";
description = "Equal to 0xcafebabe";
prefix = "IDCODE";
field {
name = "IDCode";
type = CONSTANT;
size = 32;
value = 0xcafebabe;
};
};
reg { -- FIXME: move to HW ports (in V3) or at least add descriptions
name = "Debug/Status register";
description = "Some debug stuff";
prefix = "DSR";
field {
name = "Link status";
prefix = "LSTATUS";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Link activity";
prefix = "LACT";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "DMTD Control Register";
prefix = "DMCR";
field {
name = "DMTD Phase measurement enable";
description = "1: enables DMTD phase measurement";
type = BIT;
prefix = "EN";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
field {
name = "DMTD averaging samples";
description = "Number of raw DMTD phase samples averaged in every measurement cycle";
prefix = "N_AVG";
type = SLV;
size = 12;
align = 16;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
};
};
reg {
name = "DMTD Status register";
prefix = "DMSR";
field {
name = "DMTD Phase shift value";
prefix = "PS_VAL";
size = 24;
type = SLV;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
field {
name = "DMTD Phase shift value ready";
prefix = "PS_RDY";
type = BIT;
load = LOAD_EXT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
};
};
ram {
name = "Event counters memory";
description = "RMON event counters:\
0x0 : TX PCS buffer underruns\
0x4 : RX PCS invalid 8b10b codes\
0x8 : RX PCS sync lost events\
0xc : RX PCS buffer overruns\
0x10: RX CRC errors\
0x14: RX valid frames\
0x18: RX runt frames\
0x1c: RX giant frames\
0x20: RX PCS errors\
0x24: RX dropped frames";
size = 32;
width = 32;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
prefix = "rmon_ram";
};
};
\ No newline at end of file
kernel/wbgen-regs/nic-regs.h 0 → 100644
View file @ dc7a4c3c
/*
Register definitions for slave core: White Rabbit Switch NIC's spec
* File : nic-regs.h
* Author : auto-generated by wbgen2 from nic-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE nic-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_NIC
#define __WBGEN2_REGDEFS_NIC
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: NIC Control Register */
/* definitions for field: Receive enable in reg: NIC Control Register */
#define NIC_CR_RX_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Transmit enable in reg: NIC Control Register */
#define NIC_CR_TX_EN WBGEN2_GEN_MASK(1, 1)
/* definitions for register: NIC Status Register */
/* definitions for field: Buffer Not Available in reg: NIC Status Register */
#define NIC_SR_BNA WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Frame Received in reg: NIC Status Register */
#define NIC_SR_REC WBGEN2_GEN_MASK(1, 1)
/* definitions for register: SW_Reset */
/* definitions for register: TX Descriptor 1 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 1 register 1 */
#define NIC_TX1_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX1_D1_TS_ID_SHIFT 16
#define NIC_TX1_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX1_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 1 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 1 register 2 */
#define NIC_TX1_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX1_D2_OFFSET_SHIFT 0
#define NIC_TX1_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX1_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 1 register 2 */
#define NIC_TX1_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX1_D2_LEN_SHIFT 16
#define NIC_TX1_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX1_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 1 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 1 register 3 */
#define NIC_TX1_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX1_D3_DPM_SHIFT 0
#define NIC_TX1_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX1_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 2 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 2 register 1 */
#define NIC_TX2_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX2_D1_TS_ID_SHIFT 16
#define NIC_TX2_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX2_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 2 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 2 register 2 */
#define NIC_TX2_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX2_D2_OFFSET_SHIFT 0
#define NIC_TX2_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX2_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 2 register 2 */
#define NIC_TX2_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX2_D2_LEN_SHIFT 16
#define NIC_TX2_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX2_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 2 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 2 register 3 */
#define NIC_TX2_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX2_D3_DPM_SHIFT 0
#define NIC_TX2_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX2_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 3 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 3 register 1 */
#define NIC_TX3_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX3_D1_TS_ID_SHIFT 16
#define NIC_TX3_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX3_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 3 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 3 register 2 */
#define NIC_TX3_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX3_D2_OFFSET_SHIFT 0
#define NIC_TX3_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX3_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 3 register 2 */
#define NIC_TX3_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX3_D2_LEN_SHIFT 16
#define NIC_TX3_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX3_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 3 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 3 register 3 */
#define NIC_TX3_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX3_D3_DPM_SHIFT 0
#define NIC_TX3_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX3_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 4 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 4 register 1 */
#define NIC_TX4_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX4_D1_TS_ID_SHIFT 16
#define NIC_TX4_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX4_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 4 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 4 register 2 */
#define NIC_TX4_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX4_D2_OFFSET_SHIFT 0
#define NIC_TX4_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX4_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 4 register 2 */
#define NIC_TX4_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX4_D2_LEN_SHIFT 16
#define NIC_TX4_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX4_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 4 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 4 register 3 */
#define NIC_TX4_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX4_D3_DPM_SHIFT 0
#define NIC_TX4_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX4_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 5 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 5 register 1 */
#define NIC_TX5_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX5_D1_TS_ID_SHIFT 16
#define NIC_TX5_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX5_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 5 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 5 register 2 */
#define NIC_TX5_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX5_D2_OFFSET_SHIFT 0
#define NIC_TX5_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX5_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 5 register 2 */
#define NIC_TX5_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX5_D2_LEN_SHIFT 16
#define NIC_TX5_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX5_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 5 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 5 register 3 */
#define NIC_TX5_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX5_D3_DPM_SHIFT 0
#define NIC_TX5_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX5_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 6 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 6 register 1 */
#define NIC_TX6_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX6_D1_TS_ID_SHIFT 16
#define NIC_TX6_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX6_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 6 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 6 register 2 */
#define NIC_TX6_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX6_D2_OFFSET_SHIFT 0
#define NIC_TX6_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX6_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 6 register 2 */
#define NIC_TX6_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX6_D2_LEN_SHIFT 16
#define NIC_TX6_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX6_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 6 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 6 register 3 */
#define NIC_TX6_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX6_D3_DPM_SHIFT 0
#define NIC_TX6_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX6_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 7 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 7 register 1 */
#define NIC_TX7_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX7_D1_TS_ID_SHIFT 16
#define NIC_TX7_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX7_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 7 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 7 register 2 */
#define NIC_TX7_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX7_D2_OFFSET_SHIFT 0
#define NIC_TX7_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX7_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 7 register 2 */
#define NIC_TX7_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX7_D2_LEN_SHIFT 16
#define NIC_TX7_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX7_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 7 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 7 register 3 */
#define NIC_TX7_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX7_D3_DPM_SHIFT 0
#define NIC_TX7_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX7_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: TX Descriptor 8 register 1 */
/* definitions for field: Ready in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_READY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timestamp Enable in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_TS_E WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Pad Enable in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_PAD_E WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Timestamp Frame Identifier in reg: TX Descriptor 8 register 1 */
#define NIC_TX8_D1_TS_ID_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX8_D1_TS_ID_SHIFT 16
#define NIC_TX8_D1_TS_ID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX8_D1_TS_ID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 8 register 2 */
/* definitions for field: offset in RAM--in bytes, must be aligned to 32-bit boundary in reg: TX Descriptor 8 register 2 */
#define NIC_TX8_D2_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_TX8_D2_OFFSET_SHIFT 0
#define NIC_TX8_D2_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_TX8_D2_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2) in reg: TX Descriptor 8 register 2 */
#define NIC_TX8_D2_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_TX8_D2_LEN_SHIFT 16
#define NIC_TX8_D2_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_TX8_D2_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: TX Descriptor 8 register 3 */
/* definitions for field: Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet. in reg: TX Descriptor 8 register 3 */
#define NIC_TX8_D3_DPM_MASK WBGEN2_GEN_MASK(0, 32)
#define NIC_TX8_D3_DPM_SHIFT 0
#define NIC_TX8_D3_DPM_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define NIC_TX8_D3_DPM_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: RX Descriptor 1 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX1_D1_PORT_SHIFT 8
#define NIC_RX1_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX1_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 1 register 1 */
#define NIC_RX1_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 1 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 1 register 2 */
#define NIC_RX1_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX1_D2_TS_R_SHIFT 0
#define NIC_RX1_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX1_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 1 register 2 */
#define NIC_RX1_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX1_D2_TS_F_SHIFT 28
#define NIC_RX1_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX1_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 1 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 1 register 3 */
#define NIC_RX1_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX1_D3_OFFSET_SHIFT 0
#define NIC_RX1_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX1_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 1 register 3 */
#define NIC_RX1_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX1_D3_LEN_SHIFT 16
#define NIC_RX1_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX1_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 2 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX2_D1_PORT_SHIFT 8
#define NIC_RX2_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX2_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 2 register 1 */
#define NIC_RX2_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 2 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 2 register 2 */
#define NIC_RX2_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX2_D2_TS_R_SHIFT 0
#define NIC_RX2_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX2_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 2 register 2 */
#define NIC_RX2_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX2_D2_TS_F_SHIFT 28
#define NIC_RX2_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX2_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 2 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 2 register 3 */
#define NIC_RX2_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX2_D3_OFFSET_SHIFT 0
#define NIC_RX2_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX2_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 2 register 3 */
#define NIC_RX2_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX2_D3_LEN_SHIFT 16
#define NIC_RX2_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX2_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 3 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX3_D1_PORT_SHIFT 8
#define NIC_RX3_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX3_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 3 register 1 */
#define NIC_RX3_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 3 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 3 register 2 */
#define NIC_RX3_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX3_D2_TS_R_SHIFT 0
#define NIC_RX3_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX3_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 3 register 2 */
#define NIC_RX3_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX3_D2_TS_F_SHIFT 28
#define NIC_RX3_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX3_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 3 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 3 register 3 */
#define NIC_RX3_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX3_D3_OFFSET_SHIFT 0
#define NIC_RX3_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX3_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 3 register 3 */
#define NIC_RX3_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX3_D3_LEN_SHIFT 16
#define NIC_RX3_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX3_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 4 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX4_D1_PORT_SHIFT 8
#define NIC_RX4_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX4_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 4 register 1 */
#define NIC_RX4_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 4 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 4 register 2 */
#define NIC_RX4_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX4_D2_TS_R_SHIFT 0
#define NIC_RX4_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX4_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 4 register 2 */
#define NIC_RX4_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX4_D2_TS_F_SHIFT 28
#define NIC_RX4_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX4_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 4 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 4 register 3 */
#define NIC_RX4_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX4_D3_OFFSET_SHIFT 0
#define NIC_RX4_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX4_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 4 register 3 */
#define NIC_RX4_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX4_D3_LEN_SHIFT 16
#define NIC_RX4_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX4_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 5 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX5_D1_PORT_SHIFT 8
#define NIC_RX5_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX5_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 5 register 1 */
#define NIC_RX5_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 5 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 5 register 2 */
#define NIC_RX5_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX5_D2_TS_R_SHIFT 0
#define NIC_RX5_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX5_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 5 register 2 */
#define NIC_RX5_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX5_D2_TS_F_SHIFT 28
#define NIC_RX5_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX5_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 5 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 5 register 3 */
#define NIC_RX5_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX5_D3_OFFSET_SHIFT 0
#define NIC_RX5_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX5_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 5 register 3 */
#define NIC_RX5_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX5_D3_LEN_SHIFT 16
#define NIC_RX5_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX5_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 6 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX6_D1_PORT_SHIFT 8
#define NIC_RX6_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX6_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 6 register 1 */
#define NIC_RX6_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 6 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 6 register 2 */
#define NIC_RX6_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX6_D2_TS_R_SHIFT 0
#define NIC_RX6_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX6_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 6 register 2 */
#define NIC_RX6_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX6_D2_TS_F_SHIFT 28
#define NIC_RX6_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX6_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 6 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 6 register 3 */
#define NIC_RX6_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX6_D3_OFFSET_SHIFT 0
#define NIC_RX6_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX6_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 6 register 3 */
#define NIC_RX6_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX6_D3_LEN_SHIFT 16
#define NIC_RX6_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX6_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 7 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX7_D1_PORT_SHIFT 8
#define NIC_RX7_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX7_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 7 register 1 */
#define NIC_RX7_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 7 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 7 register 2 */
#define NIC_RX7_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX7_D2_TS_R_SHIFT 0
#define NIC_RX7_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX7_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 7 register 2 */
#define NIC_RX7_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX7_D2_TS_F_SHIFT 28
#define NIC_RX7_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX7_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 7 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 7 register 3 */
#define NIC_RX7_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX7_D3_OFFSET_SHIFT 0
#define NIC_RX7_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX7_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 7 register 3 */
#define NIC_RX7_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX7_D3_LEN_SHIFT 16
#define NIC_RX7_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX7_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: RX Descriptor 8 register 1 */
/* definitions for field: Empty in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_EMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Error in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_ERROR WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block. in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_PORT_MASK WBGEN2_GEN_MASK(8, 6)
#define NIC_RX8_D1_PORT_SHIFT 8
#define NIC_RX8_D1_PORT_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define NIC_RX8_D1_PORT_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Got RX Timestamp in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_GOT_TS WBGEN2_GEN_MASK(14, 1)
/* definitions for field: RX Timestamp (possibly) incorrect in reg: RX Descriptor 8 register 1 */
#define NIC_RX8_D1_TS_INCORRECT WBGEN2_GEN_MASK(15, 1)
/* definitions for register: RX Descriptor 8 register 2 */
/* definitions for field: RX_TS_R in reg: RX Descriptor 8 register 2 */
#define NIC_RX8_D2_TS_R_MASK WBGEN2_GEN_MASK(0, 28)
#define NIC_RX8_D2_TS_R_SHIFT 0
#define NIC_RX8_D2_TS_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define NIC_RX8_D2_TS_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: RX_TS_F in reg: RX Descriptor 8 register 2 */
#define NIC_RX8_D2_TS_F_MASK WBGEN2_GEN_MASK(28, 4)
#define NIC_RX8_D2_TS_F_SHIFT 28
#define NIC_RX8_D2_TS_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define NIC_RX8_D2_TS_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: RX Descriptor 8 register 3 */
/* definitions for field: Offset in packet RAM (in bytes, 32-bit aligned) in reg: RX Descriptor 8 register 3 */
#define NIC_RX8_D3_OFFSET_MASK WBGEN2_GEN_MASK(0, 16)
#define NIC_RX8_D3_OFFSET_SHIFT 0
#define NIC_RX8_D3_OFFSET_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define NIC_RX8_D3_OFFSET_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet. in reg: RX Descriptor 8 register 3 */
#define NIC_RX8_D3_LEN_MASK WBGEN2_GEN_MASK(16, 16)
#define NIC_RX8_D3_LEN_SHIFT 16
#define NIC_RX8_D3_LEN_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define NIC_RX8_D3_LEN_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Interrupt disable register */
/* definitions for field: Receive Complete in reg: Interrupt disable register */
#define NIC_EIC_IDR_RCOMP WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Transmit Complete in reg: Interrupt disable register */
#define NIC_EIC_IDR_TCOMP WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Receive Error in reg: Interrupt disable register */
#define NIC_EIC_IDR_RXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Transmit Error in reg: Interrupt disable register */
#define NIC_EIC_IDR_TXERR WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: Receive Complete in reg: Interrupt enable register */
#define NIC_EIC_IER_RCOMP WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Transmit Complete in reg: Interrupt enable register */
#define NIC_EIC_IER_TCOMP WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Receive Error in reg: Interrupt enable register */
#define NIC_EIC_IER_RXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Transmit Error in reg: Interrupt enable register */
#define NIC_EIC_IER_TXERR WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: Receive Complete in reg: Interrupt mask register */
#define NIC_EIC_IMR_RCOMP WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Transmit Complete in reg: Interrupt mask register */
#define NIC_EIC_IMR_TCOMP WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Receive Error in reg: Interrupt mask register */
#define NIC_EIC_IMR_RXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Transmit Error in reg: Interrupt mask register */
#define NIC_EIC_IMR_TXERR WBGEN2_GEN_MASK(3, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: Receive Complete in reg: Interrupt status register */
#define NIC_EIC_ISR_RCOMP WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Transmit Complete in reg: Interrupt status register */
#define NIC_EIC_ISR_TCOMP WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Receive Error in reg: Interrupt status register */
#define NIC_EIC_ISR_RXERR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Transmit Error in reg: Interrupt status register */
#define NIC_EIC_ISR_TXERR WBGEN2_GEN_MASK(3, 1)
/* definitions for RAM: TX/RX Buffers */
#define NIC_MEM_BASE 0x00008000 /* base address */
#define NIC_MEM_BYTES 0x00008000 /* size in bytes */
#define NIC_MEM_WORDS 0x00002000 /* size in 32-bit words, 32-bit aligned */
PACKED struct NIC_WB {
/* [0x0]: REG NIC Control Register */
uint32_t CR;
/* [0x4]: REG NIC Status Register */
uint32_t SR;
/* [0x8]: REG SW_Reset */
uint32_t RESET;
/* padding to: 4 words */
uint32_t __padding_0[1];
/* [0x10]: REG TX Descriptor 1 register 1 */
uint32_t TX1_D1;
/* [0x14]: REG TX Descriptor 1 register 2 */
uint32_t TX1_D2;
/* [0x18]: REG TX Descriptor 1 register 3 */
uint32_t TX1_D3;
/* padding to: 8 words */
uint32_t __padding_1[1];
/* [0x20]: REG TX Descriptor 2 register 1 */
uint32_t TX2_D1;
/* [0x24]: REG TX Descriptor 2 register 2 */
uint32_t TX2_D2;
/* [0x28]: REG TX Descriptor 2 register 3 */
uint32_t TX2_D3;
/* padding to: 12 words */
uint32_t __padding_2[1];
/* [0x30]: REG TX Descriptor 3 register 1 */
uint32_t TX3_D1;
/* [0x34]: REG TX Descriptor 3 register 2 */
uint32_t TX3_D2;
/* [0x38]: REG TX Descriptor 3 register 3 */
uint32_t TX3_D3;
/* padding to: 16 words */
uint32_t __padding_3[1];
/* [0x40]: REG TX Descriptor 4 register 1 */
uint32_t TX4_D1;
/* [0x44]: REG TX Descriptor 4 register 2 */
uint32_t TX4_D2;
/* [0x48]: REG TX Descriptor 4 register 3 */
uint32_t TX4_D3;
/* padding to: 20 words */
uint32_t __padding_4[1];
/* [0x50]: REG TX Descriptor 5 register 1 */
uint32_t TX5_D1;
/* [0x54]: REG TX Descriptor 5 register 2 */
uint32_t TX5_D2;
/* [0x58]: REG TX Descriptor 5 register 3 */
uint32_t TX5_D3;
/* padding to: 24 words */
uint32_t __padding_5[1];
/* [0x60]: REG TX Descriptor 6 register 1 */
uint32_t TX6_D1;
/* [0x64]: REG TX Descriptor 6 register 2 */
uint32_t TX6_D2;
/* [0x68]: REG TX Descriptor 6 register 3 */
uint32_t TX6_D3;
/* padding to: 28 words */
uint32_t __padding_6[1];
/* [0x70]: REG TX Descriptor 7 register 1 */
uint32_t TX7_D1;
/* [0x74]: REG TX Descriptor 7 register 2 */
uint32_t TX7_D2;
/* [0x78]: REG TX Descriptor 7 register 3 */
uint32_t TX7_D3;
/* padding to: 32 words */
uint32_t __padding_7[1];
/* [0x80]: REG TX Descriptor 8 register 1 */
uint32_t TX8_D1;
/* [0x84]: REG TX Descriptor 8 register 2 */
uint32_t TX8_D2;
/* [0x88]: REG TX Descriptor 8 register 3 */
uint32_t TX8_D3;
/* padding to: 36 words */
uint32_t __padding_8[1];
/* [0x90]: REG RX Descriptor 1 register 1 */
uint32_t RX1_D1;
/* [0x94]: REG RX Descriptor 1 register 2 */
uint32_t RX1_D2;
/* [0x98]: REG RX Descriptor 1 register 3 */
uint32_t RX1_D3;
/* padding to: 40 words */
uint32_t __padding_9[1];
/* [0xa0]: REG RX Descriptor 2 register 1 */
uint32_t RX2_D1;
/* [0xa4]: REG RX Descriptor 2 register 2 */
uint32_t RX2_D2;
/* [0xa8]: REG RX Descriptor 2 register 3 */
uint32_t RX2_D3;
/* padding to: 44 words */
uint32_t __padding_10[1];
/* [0xb0]: REG RX Descriptor 3 register 1 */
uint32_t RX3_D1;
/* [0xb4]: REG RX Descriptor 3 register 2 */
uint32_t RX3_D2;
/* [0xb8]: REG RX Descriptor 3 register 3 */
uint32_t RX3_D3;
/* padding to: 48 words */
uint32_t __padding_11[1];
/* [0xc0]: REG RX Descriptor 4 register 1 */
uint32_t RX4_D1;
/* [0xc4]: REG RX Descriptor 4 register 2 */
uint32_t RX4_D2;
/* [0xc8]: REG RX Descriptor 4 register 3 */
uint32_t RX4_D3;
/* padding to: 52 words */
uint32_t __padding_12[1];
/* [0xd0]: REG RX Descriptor 5 register 1 */
uint32_t RX5_D1;
/* [0xd4]: REG RX Descriptor 5 register 2 */
uint32_t RX5_D2;
/* [0xd8]: REG RX Descriptor 5 register 3 */
uint32_t RX5_D3;
/* padding to: 56 words */
uint32_t __padding_13[1];
/* [0xe0]: REG RX Descriptor 6 register 1 */
uint32_t RX6_D1;
/* [0xe4]: REG RX Descriptor 6 register 2 */
uint32_t RX6_D2;
/* [0xe8]: REG RX Descriptor 6 register 3 */
uint32_t RX6_D3;
/* padding to: 60 words */
uint32_t __padding_14[1];
/* [0xf0]: REG RX Descriptor 7 register 1 */
uint32_t RX7_D1;
/* [0xf4]: REG RX Descriptor 7 register 2 */
uint32_t RX7_D2;
/* [0xf8]: REG RX Descriptor 7 register 3 */
uint32_t RX7_D3;
/* padding to: 64 words */
uint32_t __padding_15[1];
/* [0x100]: REG RX Descriptor 8 register 1 */
uint32_t RX8_D1;
/* [0x104]: REG RX Descriptor 8 register 2 */
uint32_t RX8_D2;
/* [0x108]: REG RX Descriptor 8 register 3 */
uint32_t RX8_D3;
/* padding to: 72 words */
uint32_t __padding_16[5];
/* [0x120]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x124]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x128]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0x12c]: REG Interrupt status register */
uint32_t EIC_ISR;
/* padding to: 8192 words */
uint32_t __padding_17[8116];
/* [0x8000 - 0xffff]: RAM TX/RX Buffers, 8192 32-bit words, 32-bit aligned, word-addressable */
uint32_t MEM [8192];
};
#endif
kernel/wbgen-regs/nic-regs.wb 0 → 100644
View file @ dc7a4c3c
-- -*- Mode: LUA; tab-width: 2 -*-
-- White-Rabbit NIC spec
-- author: Emilio G. Cota <cota@braap.org>
-- updated by: Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
--
-- Use wbgen2 to generate code, documentation and more.
-- wbgen2 is available at:
-- http://www.ohwr.org/projects/wishbone-gen
--
top = peripheral {
name = "White Rabbit Switch NIC's spec",
description = "This NIC is in between the endpoints and the on-board Linux CPU of the White Rabbit Switch.\
\
Operation \
~~~~~~~ \
* There's a pool of n TX descriptors and a pool of n RX descriptors. \
* In fact, we should have n for TX and m for RX since 32K / 1536 = 21.3. Anyway, to make things simple, first let's do n and n; we can fine-tune later on. \
* Software keeps track of which buffers are marked to be used with the READY/EMPTY flags. \
* Interrupts are useed by software to update the state, e.g. when frames are received or when a frame has been sent. \
* Endianness: all multi-byte registers are Little Endian \
\
Frame transmission \
~~~~~~~~~~~~~~~ \
* Enable Transmission in the Control Register \
* Store the frame in memory \
* Fill in the corresponding descriptor from the TX pool \
* Set READY bit to 1 \
* Interrupt arrives--if enabled-- and software updates stats reading the descriptor (READY has been set to 0 by the NIC). \
\
Frame reception \
~~~~~~~~~~~~~ \
* Enable Reception in the Control Register \
* Initialize a descriptor from the RX descriptors pool. Mark it as EMPTY \
* A frame is received and, if enabled, the NIC raises an interrupt \
* With EMPTY set to 0, the frame can now be copied from the NIC's memory and stats can be updated \
* Set READY bit to 1 \
\
Todo \
~~~~ \
* Descriptors in RAM, not as registers. wbgen2 doesn't support this yet. Working on it. \
Known issues \
~~~~~~~~~~~ \
* Only 32-bit aligned addresses are supported";
hdl_entity = "nic_wishbone_slave";
prefix = "nic";
reg {
name = "NIC Control Register";
prefix = "CR";
field {
name = "Receive enable";
description = "Enables the NIC to receive data";
prefix = "rx_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Transmit enable";
description = "Enables the NIC to transmit data. When reset, the internal transmit pointer points to the first entry in the TX descriptor pool";
prefix = "tx_en";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "NIC Status Register";
prefix = "SR";
field {
name = "Buffer Not Available";
prefix = "bna";
description = "No buffers were available when receiving a packet.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
load = LOAD_EXT;
};
field {
name = "Frame Received";
prefix = "rec";
description = "One or more frames have been received.\
Cleared by writing a one to this bit";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "SW_Reset";
description = "Writing to this register resets the NIC, zeroing all registers and resetting the state of the module";
prefix = "reset";
field {
name = "Software reset";
type = PASS_THROUGH;
size = 32;
};
};
irq {
name = "Receive Complete";
prefix = "rcomp";
description = "A frame has been stored in memory.";
trigger = LEVEL_1;
};
irq {
name = "Transmit Complete";
prefix = "tcomp";
description = "Frame successfully transmitted";
trigger = LEVEL_1;
};
irq {
name = "Receive Error";
prefix = "rxerr";
description = "Receive Error";
trigger = LEVEL_1;
};
irq {
name = "Transmit Error";
prefix = "txerr";
trigger = LEVEL_1;
};
-- ram {
-- name = "TX descriptors mem";
-- prefix = "dtx";
-- size = 32;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
-- ram {
-- name = "RX descriptors mem";
-- prefix = "drx";
-- size = 32;
-- width = 32;
-- access_bus = READ_WRITE;
-- access_dev = READ_WRITE;
-- };
ram {
name = "TX/RX Buffers";
prefix = "mem";
-- 8192 * 32 = 32Kb
size = 8192;
width = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
};
};
TX_desc_template =
{
reg {
name = "TX Descriptor %d register 1";
description = "1st part of TX descriptor header. ";
prefix = "tx%d_d1";
align = 4;
field {
name = "Ready";
prefix = "ready";
description = "0 - The descriptor and buffer can be manipulated. \
1 - The device owns the descriptor and will set the bit to 0 after transmission";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Error";
prefix = "error";
description = "1 - an error occured during transmission of this descriptor.\
0 - transmission was successful";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Timestamp Enable";
description = "Set to 1 if the frame has to be timestamped by the endpoint. The NIC will then generate a TX OOB block on its WRF source, containing the value of TS_ID from the descriptor. ";
prefix = "ts_e";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Pad Enable";
prefix = "pad_e";
description = "When set, short frames (< 60 bytes) are padded with zeros to 60 bytes. This doesn't include the CRC field (so the final frame length will be 64 bytes)";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
-- todo: Errors: add some more, e.g. Retry Count, Retry Limit exceeded...
field {
name = "Timestamp Frame Identifier";
prefix = "ts_id";
description = "Frame Identifier - a 16-bit value which must be unique in reasonably long time period. It's used to match the TX timestamps coming from different physical ports with the timestamped packets.";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX Descriptor %d register 2";
prefix = "tx%d_d2";
field {
name = "offset in RAM--in bytes, must be aligned to 32-bit boundary";
prefix = "offset";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Length of buffer--in bytes. Least significant bit must always be 0 (the packet size must be divisible by 2)";
prefix = "len";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "TX Descriptor %d register 3";
prefix = "tx%d_d3";
field {
prefix = "DPM";
name = "Destination Port Mask: 0x00000001 means the packet will be sent to port 0, 0x00000002 - port 1, etc. 0xffffffff means broadcast. 0x0 doesn't make any sense yet.";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
RX_desc_template = {
reg {
align=4;
name = "RX Descriptor %d register 1";
description = "Descriptor of an RX frame buffer";
prefix = "rx%d_d1";
field {
name = "Empty";
prefix = "empty";
description = "0 - Reception (or failure) has occurred on this buffer. The NIC cannot operate on the until this bit is set to 1. \
1 - The buffer is ready to be filled in with data by the NIC";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Error";
prefix = "error";
description = "Set when the the received frame contains an error (an error was indicated by the remote WRF source)";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Port number of the receiving endpoint--0 to n-1. Indicated in RX OOB block.";
prefix = "port";
type = SLV;
size = 6;
align = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Got RX Timestamp";
prefix = "GOT_TS";
description = "1 - there is a valid RX timestamp present in the TS field,\
0 - no RX timestamp";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX Timestamp (possibly) incorrect";
prefix = "TS_INCORRECT";
align = 15;
description = "1 - there is a risk that the timestamp in RX_D2 is invalid, because it was taken during counter adjustment,\
0 - RX timestamp OK.";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "RX Descriptor %d register 2";
prefix = "rx%d_d2";
field {
name = "RX_TS_R";
prefix = "TS_R";
description = "Value of the RX timestamp (rising edge bits)";
size = 28;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "RX_TS_F";
prefix = "TS_F";
description = "Value of the RX timestamp (falling edge bits)";
size = 4;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "RX Descriptor %d register 3";
prefix = "rx%d_d3";
field {
name = "Offset in packet RAM (in bytes, 32-bit aligned)";
prefix = "offset";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
},
field {
name = "Length of buffer in bytes. After reception of the packet, it's updated with the length of the received packet.";
prefix = "len";
type = SLV;
size = 16;
align = 16;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
};
function generate_descriptors(n)
local i;
for i=1,n do
local T=deepcopy(TX_desc_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
print(r.name)
end, T);
table_join(periph, T);
end
for i=1,n do
local T=deepcopy(RX_desc_template);
foreach_reg({TYPE_REG}, function(r)
r.name = string.format(r.name, i);
r.prefix = string.format(r.prefix, i);
end, T);
table_join(periph, T);
end
end
generate_descriptors(8);
kernel/wbgen-regs/ppsg-regs.h 0 → 100644
View file @ dc7a4c3c
/*
Register definitions for slave core: WR Switch PPS generator and RTC
* File : ppsg-regs.h
* Author : auto-generated by wbgen2 from ppsg-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ppsg-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_PPSG
#define __WBGEN2_REGDEFS_PPSG
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control Register */
/* definitions for field: Reset counter in reg: Control Register */
#define PPSG_CR_CNT_RST WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Enable counter in reg: Control Register */
#define PPSG_CR_CNT_EN WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Adjust offset in reg: Control Register */
#define PPSG_CR_CNT_ADJ WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Set time in reg: Control Register */
#define PPSG_CR_CNT_SET WBGEN2_GEN_MASK(3, 1)
/* definitions for field: PPS Pulse width in reg: Control Register */
#define PPSG_CR_PWIDTH_MASK WBGEN2_GEN_MASK(4, 28)
#define PPSG_CR_PWIDTH_SHIFT 4
#define PPSG_CR_PWIDTH_W(value) WBGEN2_GEN_WRITE(value, 4, 28)
#define PPSG_CR_PWIDTH_R(reg) WBGEN2_GEN_READ(reg, 4, 28)
/* definitions for register: Nanosecond counter register */
/* definitions for register: UTC Counter register (least-significant part) */
/* definitions for register: UTC Counter register (most-significant part) */
/* definitions for register: Nanosecond adjustment register */
/* definitions for register: UTC Adjustment register (least-significant part) */
/* definitions for register: UTC Adjustment register (most-significant part) */
/* definitions for register: External sync control register */
/* definitions for field: Sync to external PPS input in reg: External sync control register */
#define PPSG_ESCR_SYNC WBGEN2_GEN_MASK(0, 1)
/* definitions for field: PPS output valid in reg: External sync control register */
#define PPSG_ESCR_PPS_VALID WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Timecode output(UTC+cycles) valid in reg: External sync control register */
#define PPSG_ESCR_TM_VALID WBGEN2_GEN_MASK(2, 1)
PACKED struct PPSG_WB {
/* [0x0]: REG Control Register */
uint32_t CR;
/* [0x4]: REG Nanosecond counter register */
uint32_t CNTR_NSEC;
/* [0x8]: REG UTC Counter register (least-significant part) */
uint32_t CNTR_UTCLO;
/* [0xc]: REG UTC Counter register (most-significant part) */
uint32_t CNTR_UTCHI;
/* [0x10]: REG Nanosecond adjustment register */
uint32_t ADJ_NSEC;
/* [0x14]: REG UTC Adjustment register (least-significant part) */
uint32_t ADJ_UTCLO;
/* [0x18]: REG UTC Adjustment register (most-significant part) */
uint32_t ADJ_UTCHI;
/* [0x1c]: REG External sync control register */
uint32_t ESCR;
};
#endif
kernel/wbgen-regs/ppsg-regs.wb 0 → 100644
View file @ dc7a4c3c
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "WR Switch PPS generator and RTC";
description = "Unit generating PPS signals and acting as a UTC real-time clock";
hdl_entity = "pps_gen_wb";
prefix = "ppsg";
reg {
name = "Control Register";
prefix = "CR";
field {
name = "Reset counter";
description = "write 1: resets the counter\
write 0: no effect";
prefix = "CNT_RST";
type = MONOSTABLE;
clock = "refclk_i";
};
field {
name = "Enable counter";
description = "1: PPS counter is enabled";
prefix = "CNT_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
field {
name = "Adjust offset";
description = "write 1: Starts adjusting PPS/UTC offsets by adding the values taken from ADJ_NSEC, ADJ_UTCLO, ADJ_UTCHI registers to the current PPS counter value. These registers need to be programmed prior to update.\
write 0: no effect\
read 0: adjustment operation is done\
read 1: adjustment operation is in progress";
prefix = "CNT_ADJ";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
clock = "refclk_i";
};
field {
name = "Set time";
description = "write 1: Sets the UTC/PPS counter to values taken from ADJ_NSEC, ADJ_UTCLO, ADJ_UTCHI registers";
prefix = "CNT_SET";
type = MONOSTABLE;
clock = "refclk_i";
};
field {
name = "PPS Pulse width";
description = "Width of generated PPS pulses in 125 MHz refernce clock cycles";
prefix = "PWIDTH";
size = 28;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock= "refclk_i";
};
};
reg {
name = "Nanosecond counter register";
description = "Nanosecond part of current time, expressed as number of 125 MHz reference clock cycles";
prefix = "CNTR_NSEC";
field {
name = "Nanosecond counter";
type = SLV;
size = 28;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "UTC Counter register (least-significant part)";
description = "Lower 32 bits of current UTC time";
prefix = "CNTR_UTCLO";
field {
name = "UTC Counter";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "UTC Counter register (most-significant part)";
description = "Highest 8 bits of current UTC time";
prefix = "CNTR_UTCHI";
field {
name = "UTC Counter";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
clock = "refclk_i";
};
};
reg {
name = "Nanosecond adjustment register";
description = "Adjustment value for nanosecond counter";
prefix = "ADJ_NSEC";
field {
name = "Nanosecond adjustment";
type = PASS_THROUGH;
size = 28;
};
};
reg {
name = "UTC Adjustment register (least-significant part)";
description = "Lower 32 bits of adjustment value for UTC";
prefix = "ADJ_UTCLO";
field {
name = "UTC Counter adjustment";
type = PASS_THROUGH;
size = 32;
};
};
reg {
name = "UTC Adjustment register (most-significant part)";
description = "Highest 8 bits of adjustment value for UTC";
prefix = "ADJ_UTCHI";
field {
name = "UTC Counter adjustment";
type = PASS_THROUGH;
size = 8;
};
};
reg {
name = "External sync control register";
prefix = "ESCR";
field {
name = "Sync to external PPS input";
description = "write 1: Waits until a pulse on external PPS input arrives and re-synchronizes the PPS counter to it\
write 0: no effect\
read 1: external synchronization done\
read 0: external synchronization in progress";
type = BIT;
prefix = "SYNC";
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
clock = "refclk_i";
};
field {
name = "PPS output valid";
description = "write 1: PPS output provides reliable 1-PPS signal\
write 0: PPS output is invalid";
prefix = "PPS_VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
field {
name = "Timecode output(UTC+cycles) valid";
description = "write 1: Timecode output provides valid time\
write 0: Timecode output does not provide valid time";
prefix = "TM_VALID";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
clock = "refclk_i";
};
};
};
kernel/wbgen-regs/rtu-regs.h 0 → 100644
View file @ dc7a4c3c
/*
Register definitions for slave core: Routing Table Unit (RTU)
* File : rtu-regs.h
* Author : auto-generated by wbgen2 from rtu-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE rtu-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_RTU
#define __WBGEN2_REGDEFS_RTU
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: RTU Global Control Register */
/* definitions for field: RTU Global Enable in reg: RTU Global Control Register */
#define RTU_GCR_G_ENA WBGEN2_GEN_MASK(0, 1)
/* definitions for field: MFIFO Trigger in reg: RTU Global Control Register */
#define RTU_GCR_MFIFOTRIG WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Hash Poly in reg: RTU Global Control Register */
#define RTU_GCR_POLY_VAL_MASK WBGEN2_GEN_MASK(8, 16)
#define RTU_GCR_POLY_VAL_SHIFT 8
#define RTU_GCR_POLY_VAL_W(value) WBGEN2_GEN_WRITE(value, 8, 16)
#define RTU_GCR_POLY_VAL_R(reg) WBGEN2_GEN_READ(reg, 8, 16)
/* definitions for register: Port Select Register */
/* definitions for field: Port Select in reg: Port Select Register */
#define RTU_PSR_PORT_SEL_MASK WBGEN2_GEN_MASK(0, 8)
#define RTU_PSR_PORT_SEL_SHIFT 0
#define RTU_PSR_PORT_SEL_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define RTU_PSR_PORT_SEL_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: Number of ports in reg: Port Select Register */
#define RTU_PSR_N_PORTS_MASK WBGEN2_GEN_MASK(8, 8)
#define RTU_PSR_N_PORTS_SHIFT 8
#define RTU_PSR_N_PORTS_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define RTU_PSR_N_PORTS_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for register: Port Control Register */
/* definitions for field: Learning enable in reg: Port Control Register */
#define RTU_PCR_LEARN_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Pass all packets in reg: Port Control Register */
#define RTU_PCR_PASS_ALL WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Pass BPDUs in reg: Port Control Register */
#define RTU_PCR_PASS_BPDU WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Fix priority in reg: Port Control Register */
#define RTU_PCR_FIX_PRIO WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Priority value in reg: Port Control Register */
#define RTU_PCR_PRIO_VAL_MASK WBGEN2_GEN_MASK(4, 3)
#define RTU_PCR_PRIO_VAL_SHIFT 4
#define RTU_PCR_PRIO_VAL_W(value) WBGEN2_GEN_WRITE(value, 4, 3)
#define RTU_PCR_PRIO_VAL_R(reg) WBGEN2_GEN_READ(reg, 4, 3)
/* definitions for field: Unrecognized request behaviour in reg: Port Control Register */
#define RTU_PCR_B_UNREC WBGEN2_GEN_MASK(7, 1)
/* definitions for register: VLAN Table Register 1 */
/* definitions for field: VLAN ID in reg: VLAN Table Register 1 */
#define RTU_VTR1_VID_MASK WBGEN2_GEN_MASK(0, 12)
#define RTU_VTR1_VID_SHIFT 0
#define RTU_VTR1_VID_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define RTU_VTR1_VID_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Filtering Database ID in reg: VLAN Table Register 1 */
#define RTU_VTR1_FID_MASK WBGEN2_GEN_MASK(12, 8)
#define RTU_VTR1_FID_SHIFT 12
#define RTU_VTR1_FID_W(value) WBGEN2_GEN_WRITE(value, 12, 8)
#define RTU_VTR1_FID_R(reg) WBGEN2_GEN_READ(reg, 12, 8)
/* definitions for field: Drop in reg: VLAN Table Register 1 */
#define RTU_VTR1_DROP WBGEN2_GEN_MASK(20, 1)
/* definitions for field: Has user-defined priority in reg: VLAN Table Register 1 */
#define RTU_VTR1_HAS_PRIO WBGEN2_GEN_MASK(21, 1)
/* definitions for field: Override endpoint-assigned priority in reg: VLAN Table Register 1 */
#define RTU_VTR1_PRIO_OVERRIDE WBGEN2_GEN_MASK(22, 1)
/* definitions for field: Priority value in reg: VLAN Table Register 1 */
#define RTU_VTR1_PRIO_MASK WBGEN2_GEN_MASK(23, 3)
#define RTU_VTR1_PRIO_SHIFT 23
#define RTU_VTR1_PRIO_W(value) WBGEN2_GEN_WRITE(value, 23, 3)
#define RTU_VTR1_PRIO_R(reg) WBGEN2_GEN_READ(reg, 23, 3)
/* definitions for field: Force VLAN table entry update in reg: VLAN Table Register 1 */
#define RTU_VTR1_UPDATE WBGEN2_GEN_MASK(26, 1)
/* definitions for register: VLAN Table Register 2 */
/* definitions for field: Port Mask in reg: VLAN Table Register 2 */
#define RTU_VTR2_PORT_MASK_MASK WBGEN2_GEN_MASK(0, 32)
#define RTU_VTR2_PORT_MASK_SHIFT 0
#define RTU_VTR2_PORT_MASK_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_VTR2_PORT_MASK_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Interrupt disable register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt disable register */
#define RTU_EIC_IDR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt enable register */
#define RTU_EIC_IER_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt mask register */
#define RTU_EIC_IMR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: UFIFO Not Empty IRQ in reg: Interrupt status register */
#define RTU_EIC_ISR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
/* definitions for field: Destination MAC address least-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
#define RTU_UFIFO_R0_DMAC_LO_MASK WBGEN2_GEN_MASK(0, 32)
#define RTU_UFIFO_R0_DMAC_LO_SHIFT 0
#define RTU_UFIFO_R0_DMAC_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_UFIFO_R0_DMAC_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
/* definitions for field: Destination MAC address most-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
#define RTU_UFIFO_R1_DMAC_HI_MASK WBGEN2_GEN_MASK(0, 16)
#define RTU_UFIFO_R1_DMAC_HI_SHIFT 0
#define RTU_UFIFO_R1_DMAC_HI_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define RTU_UFIFO_R1_DMAC_HI_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
/* definitions for field: Source MAC address least-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
#define RTU_UFIFO_R2_SMAC_LO_MASK WBGEN2_GEN_MASK(0, 32)
#define RTU_UFIFO_R2_SMAC_LO_SHIFT 0
#define RTU_UFIFO_R2_SMAC_LO_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_UFIFO_R2_SMAC_LO_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
/* definitions for field: Source MAC address most-significant part in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
#define RTU_UFIFO_R3_SMAC_HI_MASK WBGEN2_GEN_MASK(0, 16)
#define RTU_UFIFO_R3_SMAC_HI_SHIFT 0
#define RTU_UFIFO_R3_SMAC_HI_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define RTU_UFIFO_R3_SMAC_HI_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
/* definitions for field: VLAN Identifier in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_VID_MASK WBGEN2_GEN_MASK(0, 12)
#define RTU_UFIFO_R4_VID_SHIFT 0
#define RTU_UFIFO_R4_VID_W(value) WBGEN2_GEN_WRITE(value, 0, 12)
#define RTU_UFIFO_R4_VID_R(reg) WBGEN2_GEN_READ(reg, 0, 12)
/* definitions for field: Priority in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_PRIO_MASK WBGEN2_GEN_MASK(12, 3)
#define RTU_UFIFO_R4_PRIO_SHIFT 12
#define RTU_UFIFO_R4_PRIO_W(value) WBGEN2_GEN_WRITE(value, 12, 3)
#define RTU_UFIFO_R4_PRIO_R(reg) WBGEN2_GEN_READ(reg, 12, 3)
/* definitions for field: Port ID in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_PID_MASK WBGEN2_GEN_MASK(16, 8)
#define RTU_UFIFO_R4_PID_SHIFT 16
#define RTU_UFIFO_R4_PID_W(value) WBGEN2_GEN_WRITE(value, 16, 8)
#define RTU_UFIFO_R4_PID_R(reg) WBGEN2_GEN_READ(reg, 16, 8)
/* definitions for field: VID valid in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_HAS_VID WBGEN2_GEN_MASK(24, 1)
/* definitions for field: PRIO valid in reg: FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
#define RTU_UFIFO_R4_HAS_PRIO WBGEN2_GEN_MASK(25, 1)
/* definitions for register: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
#define RTU_UFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
#define RTU_UFIFO_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 7)
#define RTU_UFIFO_CSR_USEDW_SHIFT 0
#define RTU_UFIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 7)
#define RTU_UFIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 7)
/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
/* definitions for field: Address/data select in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
#define RTU_MFIFO_R0_AD_SEL WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
/* definitions for field: Address/data value in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
#define RTU_MFIFO_R1_AD_VAL_MASK WBGEN2_GEN_MASK(0, 32)
#define RTU_MFIFO_R1_AD_VAL_SHIFT 0
#define RTU_MFIFO_R1_AD_VAL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define RTU_MFIFO_R1_AD_VAL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
#define RTU_MFIFO_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 6)
#define RTU_MFIFO_CSR_USEDW_SHIFT 0
#define RTU_MFIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define RTU_MFIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for RAM: Aging bitmap for main hashtable */
#define RTU_ARAM_BASE 0x00000400 /* base address */
#define RTU_ARAM_BYTES 0x00000400 /* size in bytes */
#define RTU_ARAM_WORDS 0x00000100 /* size in 32-bit words, 32-bit aligned */
PACKED struct RTU_WB {
/* [0x0]: REG RTU Global Control Register */
uint32_t GCR;
/* [0x4]: REG Port Select Register */
uint32_t PSR;
/* [0x8]: REG Port Control Register */
uint32_t PCR;
/* [0xc]: REG VLAN Table Register 1 */
uint32_t VTR1;
/* [0x10]: REG VLAN Table Register 2 */
uint32_t VTR2;
/* padding to: 8 words */
uint32_t __padding_0[3];
/* [0x20]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x24]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x28]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0x2c]: REG Interrupt status register */
uint32_t EIC_ISR;
/* [0x30]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 0 */
uint32_t UFIFO_R0;
/* [0x34]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 1 */
uint32_t UFIFO_R1;
/* [0x38]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 2 */
uint32_t UFIFO_R2;
/* [0x3c]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 3 */
uint32_t UFIFO_R3;
/* [0x40]: REG FIFO 'Unrecognized request FIFO (UFIFO)' data output register 4 */
uint32_t UFIFO_R4;
/* [0x44]: REG FIFO 'Unrecognized request FIFO (UFIFO)' control/status register */
uint32_t UFIFO_CSR;
/* [0x48]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 0 */
uint32_t MFIFO_R0;
/* [0x4c]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' data input register 1 */
uint32_t MFIFO_R1;
/* [0x50]: REG FIFO 'Main hashtable CPU access FIFO (MFIFO)' control/status register */
uint32_t MFIFO_CSR;
/* padding to: 256 words */
uint32_t __padding_1[235];
/* [0x400 - 0x7ff]: RAM Aging bitmap for main hashtable, 256 32-bit words, 32-bit aligned, word-addressable */
uint32_t ARAM [256];
};
#endif
kernel/wbgen-regs/rtu-regs.wb 0 → 100644
View file @ dc7a4c3c
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Routing Table Unit (RTU)";
prefix = "rtu";
hdl_entity="rtu_wishbone_slave";
-- Port Configuration Register
reg {
name = "RTU Global Control Register";
description = "Control register containing global (port-independent) settings of the RTU.";
prefix = "GCR";
field {
name = "RTU Global Enable";
description = "Global RTU enable bit. Overrides all port settings.\
0: RTU is disabled. All packets are dropped.\
1: RTU is enabled.";
type = BIT;
prefix = "G_ENA";
access_dev = READ_ONLY;
access_bus = READ_WRITE;
clock = "clk_match_i";
};
field {
name = "MFIFO Trigger";
description = "write 1: triggers a flush of MFIFO into the hash table (blocks the RTU for a few cycles)\
write 0: no effect\
read 1: MFIFO is busy\
read 0: MFIFO is idle";
prefix = "MFIFOTRIG";
type = BIT;
load = LOAD_EXT;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
clock = "clk_match_i";
};
field {
name = "Hash Poly";
description = "Determines the polynomial used for hash computation. Currently available: 0x1021, 0x8005, 0x0589 ";
type = SLV;
prefix = "POLY_VAL";
align = 8;
size = 16 ;
access_dev = READ_ONLY;
access_bus = READ_WRITE;
clock = "clk_match_i";
};
};
reg {
name = "Port Select Register";
description = "Selects the port to control through the PCR register";
prefix = "PSR";
field {
name = "Port Select";
prefix = "PORT_SEL";
description = "Selected Port";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Number of ports";
prefix = "N_PORTS";
description = "Number of RTU ports compiled in.";
size = 8;
type = SLV;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Port Control Register";
description = "Register controlling the mode of the RTU port selected by PSELR register.";
prefix = "PCR";
field {
name = "Learning enable";
description = "1: enables learning process on this port. Unrecognized requests will be put into UFIFO\
0: disables learning. Unrecognized requests will be either broadcast or dropped.";
prefix = "LEARN_EN";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Pass all packets";
description = "1: all packets are passed (depending on the rules in RT table). \
0: all packets are dropped on this port.";
prefix = "PASS_ALL";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Pass BPDUs";
description = "1: BPDU packets (with dst MAC 01:80:c2:00:00:00) are passed according to RT rules. This setting overrides PASS_ALL.\
0: BPDU packets are passed according to RTU rules only if PASS_ALL is set.[ML by modified]";
prefix = "PASS_BPDU";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Fix priority";
description = "1: Port has fixed priority of value PRIO_VAL. It overrides the priority coming from the endpoint\
0: Use priority from the endpoint";
prefix = "FIX_PRIO";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Priority value";
description = "Fixed priority value for the port. Used instead the endpoint-assigned priority when FIX_PRIO = 1";
prefix = "PRIO_VAL";
type = SLV;
align = 4;
size =3 ;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
field {
name = "Unrecognized request behaviour";
description = "Sets the port behaviour for all unrecognized requests:\
0: packet is dropped\
1: packet is broadcast";
prefix = "B_UNREC";
type = BIT;
access_dev = READ_WRITE;
access_bus = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "VLAN Table Register 1";
prefix = "VTR1";
field {
prefix = "VID";
name = "VLAN ID";
size = 12;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
prefix = "FID";
name = "Filtering Database ID";
description = "Assigns the VID to a particular filtering database";
size = 8;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
prefix = "DROP";
name = "Drop";
description = "1: drop all packets belonging to this VLAN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
prefix = "HAS_PRIO";
name = "Has user-defined priority";
description = "1: VLAN has user-defined priority";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
prefix = "PRIO_OVERRIDE";
name = "Override endpoint-assigned priority";
description = "1: always take the priority from the PRIO field, regardless of the priority value assigned at the endpoint. ";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
prefix = "PRIO";
name = "Priority value";
type = SLV;
size = 3;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
prefix = "UPDATE";
name = "Force VLAN table entry update";
description = "write 1: flush VTR1 and VTR2 registers to VLAN table entry designated in VTR1.VID";
type = MONOSTABLE;
}
};
reg {
prefix = "VTR2";
name = "VLAN Table Register 2";
field {
name = "Port Mask";
prefix = "PORT_MASK";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
irq {
name = "UFIFO Not Empty IRQ";
description = "Interrupt active when there are some requests in UFIFO.";
prefix = "nempty";
trigger = LEVEL_0;
};
fifo_reg {
name = "Unrecognized request FIFO (UFIFO)";
description = "FIFO containing all RTU requests for which matching entries haven't been found. CPU reads these requests,\
evaluates them and updates the RTU tables accordingly.";
prefix = "UFIFO";
direction = CORE_TO_BUS;
size = 128;
flags_dev = {FIFO_FULL, FIFO_EMPTY};
flags_bus = {FIFO_EMPTY, FIFO_COUNT};
--clock = "clk_match_i";
-- clock = ""; - make it asynchronous if you want
field {
name = "Destination MAC address least-significant part";
description = "Bits [31:0] of packet destination MAC address";
prefix = "DMAC_LO";
type = SLV;
size = 32;
};
field {
name = "Destination MAC address most-significant part";
description = "Bits [47:32] of packet destination MAC address";
prefix = "DMAC_HI";
type = SLV;
size = 16;
};
field {
name = "Source MAC address least-significant part";
description = "Bits [31:0] of packet source MAC address";
prefix = "SMAC_LO";
type = SLV;
size = 32;
};
field {
name = "Source MAC address most-significant part";
description = "Bits [47:32] of packet source MAC address";
prefix = "SMAC_HI";
type = SLV;
size = 16;
};
field {
name = "VLAN Identifier";
description = "VLAN ID of the packet (from the endpoint)";
prefix = "VID";
size = 12;
type = SLV;
align = 32;
};
field {
name = "Priority";
description = "Priority value (from the endpoint)";
prefix = "PRIO";
size = 3;
align = 4;
type = SLV;
};
field {
name = "Port ID";
description = "Identifier of RTU port to which came the request.";
prefix = "PID";
size = 8;
align = 8;
type = SLV;
};
field {
name = "VID valid";
description = "1: VID value is valid\
0: packet had no VLAN ID";
prefix = "HAS_VID";
align = 4;
type = BIT;
};
field {
name = "PRIO valid";
description = "1: PRIO value is valid\
0: packet had no priority assigned";
prefix = "HAS_PRIO";
type = BIT;
};
};
ram {
name = "Aging bitmap for main hashtable";
description = "Each bit in this memory reflects the state of corresponding entry in main hashtable:\
0: entry wasn't matched\
1: entry was matched at least once.\
CPU reads this bitmap and subsequently clears it every few seconds to update the aging counters.";
prefix = "ARAM";
width = 32;
size = 8192 / 32; -- 8192 bits
access_dev = READ_WRITE;
access_bus = READ_WRITE;
--[changed 6/10/2010] clock = "clk_match_i";
--clock = "clk_match_i"; --async?
};
fifo_reg {
name = "Main hashtable CPU access FIFO (MFIFO)";
description = "FIFO for writing to main hashtable";
prefix = "MFIFO";
direction = BUS_TO_CORE;
size = 64;
flags_dev = {FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_EMPTY, FIFO_FULL, FIFO_COUNT};
field {
name = "Address/data select";
description = "1: AD_VAL contains new memory address\
0: AD_VAL contains data word to be written at current memory address. Then, the address is incremented";
prefix = "AD_SEL";
type = BIT;
};
field {
name = "Address/data value";
description = "Value of new memory address (when AD_SEL = 1) or data word to be written (when AD_SEL = 0)";
prefix = "AD_VAL";
type = SLV;
align =32;
size = 32;
};
clock = "clk_match_i";
};
};
kernel/wbgen-regs/softpll-regs.h 0 → 100644
View file @ dc7a4c3c
/*
Register definitions for slave core: WR Softcore PLL
* File : softpll-regs.h
* Author : auto-generated by wbgen2 from softpll-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE softpll-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_SOFTPLL
#define __WBGEN2_REGDEFS_SOFTPLL
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: SPLL Control/Status Register */
/* definitions for field: Period detector reference select in reg: SPLL Control/Status Register */
#define SPLL_CSR_PER_SEL_MASK WBGEN2_GEN_MASK(0, 6)
#define SPLL_CSR_PER_SEL_SHIFT 0
#define SPLL_CSR_PER_SEL_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define SPLL_CSR_PER_SEL_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for field: Number of reference channels (max: 32) in reg: SPLL Control/Status Register */
#define SPLL_CSR_N_REF_MASK WBGEN2_GEN_MASK(8, 6)
#define SPLL_CSR_N_REF_SHIFT 8
#define SPLL_CSR_N_REF_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define SPLL_CSR_N_REF_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for field: Number of output channels (max: 8) in reg: SPLL Control/Status Register */
#define SPLL_CSR_N_OUT_MASK WBGEN2_GEN_MASK(16, 3)
#define SPLL_CSR_N_OUT_SHIFT 16
#define SPLL_CSR_N_OUT_W(value) WBGEN2_GEN_WRITE(value, 16, 3)
#define SPLL_CSR_N_OUT_R(reg) WBGEN2_GEN_READ(reg, 16, 3)
/* definitions for field: Enable Period Measurement in reg: SPLL Control/Status Register */
#define SPLL_CSR_PER_EN WBGEN2_GEN_MASK(19, 1)
/* definitions for register: External Clock Control Register */
/* definitions for field: Enable External Clock BB Detector in reg: External Clock Control Register */
#define SPLL_ECCR_EXT_EN WBGEN2_GEN_MASK(0, 1)
/* definitions for field: External Clock Input Available in reg: External Clock Control Register */
#define SPLL_ECCR_EXT_SUPPORTED WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Enable PPS/phase alignment in reg: External Clock Control Register */
#define SPLL_ECCR_ALIGN_EN WBGEN2_GEN_MASK(2, 1)
/* definitions for field: PPS/phase alignment done in reg: External Clock Control Register */
#define SPLL_ECCR_ALIGN_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for field: External Clock Reference Present in reg: External Clock Control Register */
#define SPLL_ECCR_EXT_REF_PRESENT WBGEN2_GEN_MASK(4, 1)
/* definitions for register: DMTD Clock Control Register */
/* definitions for field: DMTD Clock Undersampling Divider in reg: DMTD Clock Control Register */
#define SPLL_DCCR_GATE_DIV_MASK WBGEN2_GEN_MASK(0, 6)
#define SPLL_DCCR_GATE_DIV_SHIFT 0
#define SPLL_DCCR_GATE_DIV_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define SPLL_DCCR_GATE_DIV_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for register: Reference Channel Undersampling Enable Register */
/* definitions for field: Reference Channel Undersampling Enable in reg: Reference Channel Undersampling Enable Register */
#define SPLL_RCGER_GATE_SEL_MASK WBGEN2_GEN_MASK(0, 32)
#define SPLL_RCGER_GATE_SEL_SHIFT 0
#define SPLL_RCGER_GATE_SEL_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SPLL_RCGER_GATE_SEL_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Output Channel Control Register */
/* definitions for field: Output Channel HW enable flag in reg: Output Channel Control Register */
#define SPLL_OCCR_OUT_EN_MASK WBGEN2_GEN_MASK(0, 8)
#define SPLL_OCCR_OUT_EN_SHIFT 0
#define SPLL_OCCR_OUT_EN_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define SPLL_OCCR_OUT_EN_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for field: Output Channel locked flag in reg: Output Channel Control Register */
#define SPLL_OCCR_OUT_LOCK_MASK WBGEN2_GEN_MASK(8, 8)
#define SPLL_OCCR_OUT_LOCK_SHIFT 8
#define SPLL_OCCR_OUT_LOCK_W(value) WBGEN2_GEN_WRITE(value, 8, 8)
#define SPLL_OCCR_OUT_LOCK_R(reg) WBGEN2_GEN_READ(reg, 8, 8)
/* definitions for register: Reference Channel Enable Register */
/* definitions for register: Output Channel Enable Register */
/* definitions for register: HPLL Period Error */
/* definitions for field: Period error value in reg: HPLL Period Error */
#define SPLL_PER_HPLL_ERROR_MASK WBGEN2_GEN_MASK(0, 16)
#define SPLL_PER_HPLL_ERROR_SHIFT 0
#define SPLL_PER_HPLL_ERROR_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define SPLL_PER_HPLL_ERROR_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: Period Error Valid in reg: HPLL Period Error */
#define SPLL_PER_HPLL_VALID WBGEN2_GEN_MASK(16, 1)
/* definitions for register: Helper DAC Output */
/* definitions for register: Main DAC Output */
/* definitions for field: DAC value in reg: Main DAC Output */
#define SPLL_DAC_MAIN_VALUE_MASK WBGEN2_GEN_MASK(0, 16)
#define SPLL_DAC_MAIN_VALUE_SHIFT 0
#define SPLL_DAC_MAIN_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define SPLL_DAC_MAIN_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for field: DAC select in reg: Main DAC Output */
#define SPLL_DAC_MAIN_DAC_SEL_MASK WBGEN2_GEN_MASK(16, 4)
#define SPLL_DAC_MAIN_DAC_SEL_SHIFT 16
#define SPLL_DAC_MAIN_DAC_SEL_W(value) WBGEN2_GEN_WRITE(value, 16, 4)
#define SPLL_DAC_MAIN_DAC_SEL_R(reg) WBGEN2_GEN_READ(reg, 16, 4)
/* definitions for register: Deglitcher threshold */
/* definitions for register: Debug FIFO Register - SPLL side */
/* definitions for field: Debug Value in reg: Debug FIFO Register - SPLL side */
#define SPLL_DFR_SPLL_VALUE_MASK WBGEN2_GEN_MASK(0, 31)
#define SPLL_DFR_SPLL_VALUE_SHIFT 0
#define SPLL_DFR_SPLL_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 31)
#define SPLL_DFR_SPLL_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 31)
/* definitions for field: End-of-Sample in reg: Debug FIFO Register - SPLL side */
#define SPLL_DFR_SPLL_EOS_MASK WBGEN2_GEN_MASK(31, 1)
#define SPLL_DFR_SPLL_EOS_SHIFT 31
#define SPLL_DFR_SPLL_EOS_W(value) WBGEN2_GEN_WRITE(value, 31, 1)
#define SPLL_DFR_SPLL_EOS_R(reg) WBGEN2_GEN_READ(reg, 31, 1)
/* definitions for register: Interrupt disable register */
/* definitions for field: Got a tag in reg: Interrupt disable register */
#define SPLL_EIC_IDR_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: Got a tag in reg: Interrupt enable register */
#define SPLL_EIC_IER_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: Got a tag in reg: Interrupt mask register */
#define SPLL_EIC_IMR_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: Got a tag in reg: Interrupt status register */
#define SPLL_EIC_ISR_TAG WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Debug FIFO Register - Host side' data output register 0 */
/* definitions for field: Value in reg: FIFO 'Debug FIFO Register - Host side' data output register 0 */
#define SPLL_DFR_HOST_R0_VALUE_MASK WBGEN2_GEN_MASK(0, 32)
#define SPLL_DFR_HOST_R0_VALUE_SHIFT 0
#define SPLL_DFR_HOST_R0_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define SPLL_DFR_HOST_R0_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Debug FIFO Register - Host side' data output register 1 */
/* definitions for field: Seq ID in reg: FIFO 'Debug FIFO Register - Host side' data output register 1 */
#define SPLL_DFR_HOST_R1_SEQ_ID_MASK WBGEN2_GEN_MASK(0, 16)
#define SPLL_DFR_HOST_R1_SEQ_ID_SHIFT 0
#define SPLL_DFR_HOST_R1_SEQ_ID_W(value) WBGEN2_GEN_WRITE(value, 0, 16)
#define SPLL_DFR_HOST_R1_SEQ_ID_R(reg) WBGEN2_GEN_READ(reg, 0, 16)
/* definitions for register: FIFO 'Debug FIFO Register - Host side' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Debug FIFO Register - Host side' control/status register */
#define SPLL_DFR_HOST_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Debug FIFO Register - Host side' control/status register */
#define SPLL_DFR_HOST_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Debug FIFO Register - Host side' control/status register */
#define SPLL_DFR_HOST_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 13)
#define SPLL_DFR_HOST_CSR_USEDW_SHIFT 0
#define SPLL_DFR_HOST_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 13)
#define SPLL_DFR_HOST_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 13)
/* definitions for register: FIFO 'Tag Readout Register' data output register 0 */
/* definitions for field: Tag value in reg: FIFO 'Tag Readout Register' data output register 0 */
#define SPLL_TRR_R0_VALUE_MASK WBGEN2_GEN_MASK(0, 24)
#define SPLL_TRR_R0_VALUE_SHIFT 0
#define SPLL_TRR_R0_VALUE_W(value) WBGEN2_GEN_WRITE(value, 0, 24)
#define SPLL_TRR_R0_VALUE_R(reg) WBGEN2_GEN_READ(reg, 0, 24)
/* definitions for field: Channel ID in reg: FIFO 'Tag Readout Register' data output register 0 */
#define SPLL_TRR_R0_CHAN_ID_MASK WBGEN2_GEN_MASK(24, 7)
#define SPLL_TRR_R0_CHAN_ID_SHIFT 24
#define SPLL_TRR_R0_CHAN_ID_W(value) WBGEN2_GEN_WRITE(value, 24, 7)
#define SPLL_TRR_R0_CHAN_ID_R(reg) WBGEN2_GEN_READ(reg, 24, 7)
/* definitions for field: Discontinuous bit in reg: FIFO 'Tag Readout Register' data output register 0 */
#define SPLL_TRR_R0_DISC WBGEN2_GEN_MASK(31, 1)
/* definitions for register: FIFO 'Tag Readout Register' control/status register */
/* definitions for field: FIFO empty flag in reg: FIFO 'Tag Readout Register' control/status register */
#define SPLL_TRR_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
PACKED struct SPLL_WB {
/* [0x0]: REG SPLL Control/Status Register */
uint32_t CSR;
/* [0x4]: REG External Clock Control Register */
uint32_t ECCR;
/* [0x8]: REG DMTD Clock Control Register */
uint32_t DCCR;
/* [0xc]: REG Reference Channel Undersampling Enable Register */
uint32_t RCGER;
/* [0x10]: REG Output Channel Control Register */
uint32_t OCCR;
/* [0x14]: REG Reference Channel Enable Register */
uint32_t RCER;
/* [0x18]: REG Output Channel Enable Register */
uint32_t OCER;
/* [0x1c]: REG HPLL Period Error */
uint32_t PER_HPLL;
/* [0x20]: REG Helper DAC Output */
uint32_t DAC_HPLL;
/* [0x24]: REG Main DAC Output */
uint32_t DAC_MAIN;
/* [0x28]: REG Deglitcher threshold */
uint32_t DEGLITCH_THR;
/* [0x2c]: REG Debug FIFO Register - SPLL side */
uint32_t DFR_SPLL;
/* padding to: 16 words */
uint32_t __padding_0[4];
/* [0x40]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x44]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x48]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0x4c]: REG Interrupt status register */
uint32_t EIC_ISR;
/* [0x50]: REG FIFO 'Debug FIFO Register - Host side' data output register 0 */
uint32_t DFR_HOST_R0;
/* [0x54]: REG FIFO 'Debug FIFO Register - Host side' data output register 1 */
uint32_t DFR_HOST_R1;
/* [0x58]: REG FIFO 'Debug FIFO Register - Host side' control/status register */
uint32_t DFR_HOST_CSR;
/* [0x5c]: REG FIFO 'Tag Readout Register' data output register 0 */
uint32_t TRR_R0;
/* [0x60]: REG FIFO 'Tag Readout Register' control/status register */
uint32_t TRR_CSR;
};
#endif
kernel/wbgen-regs/softpll-regs.wb 0 → 100644
View file @ dc7a4c3c
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "WR Softcore PLL";
hdl_entity = "spll_wb_slave";
prefix = "spll";
reg {
name = "SPLL Control/Status Register";
prefix = "CSR";
field {
align = 8;
name = "Period detector reference select";
prefix = "PER_SEL";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
align = 8;
name = "Number of reference channels (max: 32)";
prefix = "N_REF";
type = SLV;
size = 6;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
align = 8;
name = "Number of output channels (max: 8)";
prefix = "N_OUT";
type = SLV;
size = 3;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Enable Period Measurement";
prefix = "PER_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
---------------------------------------------
-- External clock input
---------------------------------------------
reg {
name = "External Clock Control Register";
prefix = "ECCR";
field {
name = "Enable External Clock BB Detector";
prefix = "EXT_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "External Clock Input Available";
description = "1: This instance of wr_softpll_ng supports external 10MHz clock input\
0: no support for external 10 MHz clock input.";
prefix = "EXT_SUPPORTED";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Enable PPS/phase alignment";
description = "write 1: starts aligning the external and local oscillator clock edges to be in phase\
right after the pulse on SYNC (PPS) input.\
write 0: no effect.";
prefix = "ALIGN_EN";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "PPS/phase alignment done";
description = "1: phase alignment triggered by writing to ALIGN_EN done.\
0: phase alignment in progress.";
prefix = "ALIGN_DONE";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "External Clock Reference Present";
description = "1: Reference clock present on the input\
0: reference input dead";
prefix = "EXT_REF_PRESENT";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
---------------------------------------------
-- DMTD gating/undersampling configuration
---------------------------------------------
reg {
name = "DMTD Clock Control Register";
prefix = "DCCR";
field {
name = "DMTD Clock Undersampling Divider";
prefix = "GATE_DIV";
size = 6;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reference Channel Undersampling Enable Register";
prefix = "RCGER";
field {
name = "Reference Channel Undersampling Enable";
prefix = "GATE_SEL";
size = 32;
type = PASS_THROUGH;
};
};
reg {
name = "Output Channel Control Register";
prefix = "OCCR";
field {
align = 8;
name = "Output Channel HW enable flag";
prefix = "OUT_EN";
type = SLV;
size = 8;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Output Channel locked flag";
prefix = "OUT_LOCK";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Reference Channel Enable Register";
prefix = "RCER";
field {
name = "Reference Channel Enable";
description = "write 1: enables tag generation on the input channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "Output Channel Enable Register";
prefix = "OCER";
field {
name = "Output Channel Enable";
description = "write 1: enables tag generation on the output channel corresponding to the written bit\
write 0: disables tag generation";
type = SLV;
size = 8;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
reg {
name = "HPLL Period Error";
prefix = "PER_HPLL";
field {
name = "Period error value";
prefix = "ERROR";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
ack_read = "tag_hpll_rd_period_o";
};
field {
name = "Period Error Valid";
prefix = "VALID";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Helper DAC Output";
prefix = "DAC_HPLL";
field {
name = "DAC value";
type = PASS_THROUGH;
size = 16;
};
};
reg {
name = "Main DAC Output";
prefix = "DAC_MAIN";
field {
name = "DAC value";
prefix = "VALUE";
type = PASS_THROUGH;
size = 16;
};
field {
name = "DAC select";
prefix = "DAC_SEL";
description = "Selects the output DAC to be updated with VALUE";
type = PASS_THROUGH;
size = 4;
};
};
reg {
name = "Deglitcher threshold";
prefix = "DEGLITCH_THR";
field {
name = "Threshold";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Debug FIFO Register - SPLL side";
prefix = "DFR_SPLL";
field {
name = "Debug Value";
prefix = "VALUE";
size = 31;
type = PASS_THROUGH;
};
field {
name = "End-of-Sample";
prefix = "EOS";
size = 1;
type = PASS_THROUGH;
};
};
fifo_reg {
name = "Debug FIFO Register - Host side";
prefix = "DFR_HOST";
direction = CORE_TO_BUS;
size = 8192;
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
field {
name = "Value";
prefix = "VALUE";
type = SLV;
size = 32;
};
field {
name = "Seq ID";
prefix = "SEQ_ID";
type = SLV;
size = 16;
};
};
fifo_reg {
name = "Tag Readout Register";
prefix = "TRR";
direction = CORE_TO_BUS;
size = 32;
flags_dev = {FIFO_FULL, FIFO_EMPTY};
flags_bus = {FIFO_EMPTY};
field {
name = "Tag value";
prefix = "VALUE";
type = SLV;
size = 24;
};
field {
name = "Channel ID";
description = "Tagged Channel ID: 0-31: reference tags, 32-47: output tags";
prefix = "CHAN_ID";
type = SLV;
size = 7;
};
field {
name = "Discontinuous bit";
prefix = "DISC";
description = "1: previous tag has been dropped due to FIFO overflow";
type = BIT;
};
};
irq {
name = "Got a tag";
prefix = "TAG";
trigger = LEVEL_1;
};
};
kernel/wbgen-regs/tstamp-regs.h 0 → 100644
View file @ dc7a4c3c
/*
Register definitions for slave core: Shared TX Timestamping Unit (TXTSU)
* File : tstamp-regs.h
* Author : auto-generated by wbgen2 from tstamp-regs.wb
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tstamp-regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_TSTAMP
#define __WBGEN2_REGDEFS_TSTAMP
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Interrupt disable register */
/* definitions for field: TXTSU fifo not-empty in reg: Interrupt disable register */
#define TXTSU_EIC_IDR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: TXTSU fifo not-empty in reg: Interrupt enable register */
#define TXTSU_EIC_IER_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: TXTSU fifo not-empty in reg: Interrupt mask register */
#define TXTSU_EIC_IMR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: TXTSU fifo not-empty in reg: Interrupt status register */
#define TXTSU_EIC_ISR_NEMPTY WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 0 */
/* definitions for field: Rising edge timestamp in reg: FIFO 'Timestamp FIFO' data output register 0 */
#define TXTSU_TSF_R0_VAL_R_MASK WBGEN2_GEN_MASK(0, 28)
#define TXTSU_TSF_R0_VAL_R_SHIFT 0
#define TXTSU_TSF_R0_VAL_R_W(value) WBGEN2_GEN_WRITE(value, 0, 28)
#define TXTSU_TSF_R0_VAL_R_R(reg) WBGEN2_GEN_READ(reg, 0, 28)
/* definitions for field: Falling edge timestamp in reg: FIFO 'Timestamp FIFO' data output register 0 */
#define TXTSU_TSF_R0_VAL_F_MASK WBGEN2_GEN_MASK(28, 4)
#define TXTSU_TSF_R0_VAL_F_SHIFT 28
#define TXTSU_TSF_R0_VAL_F_W(value) WBGEN2_GEN_WRITE(value, 28, 4)
#define TXTSU_TSF_R0_VAL_F_R(reg) WBGEN2_GEN_READ(reg, 28, 4)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 1 */
/* definitions for field: Physical port ID in reg: FIFO 'Timestamp FIFO' data output register 1 */
#define TXTSU_TSF_R1_PID_MASK WBGEN2_GEN_MASK(0, 5)
#define TXTSU_TSF_R1_PID_SHIFT 0
#define TXTSU_TSF_R1_PID_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define TXTSU_TSF_R1_PID_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Frame ID in reg: FIFO 'Timestamp FIFO' data output register 1 */
#define TXTSU_TSF_R1_FID_MASK WBGEN2_GEN_MASK(16, 16)
#define TXTSU_TSF_R1_FID_SHIFT 16
#define TXTSU_TSF_R1_FID_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define TXTSU_TSF_R1_FID_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: FIFO 'Timestamp FIFO' data output register 2 */
/* definitions for field: Timestamp (possibly) incorrect in reg: FIFO 'Timestamp FIFO' data output register 2 */
#define TXTSU_TSF_R2_INCORRECT WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'Timestamp FIFO' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Timestamp FIFO' control/status register */
#define TXTSU_TSF_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Timestamp FIFO' control/status register */
#define TXTSU_TSF_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Timestamp FIFO' control/status register */
#define TXTSU_TSF_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define TXTSU_TSF_CSR_USEDW_SHIFT 0
#define TXTSU_TSF_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define TXTSU_TSF_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
PACKED struct TXTSU_WB {
/* [0x0]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x4]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x8]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0xc]: REG Interrupt status register */
uint32_t EIC_ISR;
/* [0x10]: REG FIFO 'Timestamp FIFO' data output register 0 */
uint32_t TSF_R0;
/* [0x14]: REG FIFO 'Timestamp FIFO' data output register 1 */
uint32_t TSF_R1;
/* [0x18]: REG FIFO 'Timestamp FIFO' data output register 2 */
uint32_t TSF_R2;
/* [0x1c]: REG FIFO 'Timestamp FIFO' control/status register */
uint32_t TSF_CSR;
};
#endif
kernel/wbgen-regs/tstamp-regs.wb 0 → 100644
View file @ dc7a4c3c
-- -*- Mode: LUA; tab-width: 2 -*-
peripheral {
name = "Shared TX Timestamping Unit (TXTSU)";
prefix="txtsu";
hdl_entity="wrsw_txtsu_wb";
-- TXTSU shared FIFO
fifo_reg {
size = 256; -- or more. We'll see :)
direction = CORE_TO_BUS;
prefix = "tsf";
name = "Timestamp FIFO";
description = "This FIFO holds the TX packet timestamps gathered from all switch endpoints. Each entry contains a single timestamp value consisting of 2 numbers:\
- VAL_R - the timestamp taken at rising clock edge. This is the main timestamp value\
- VAL_F - few LSBs of timestamp taken at falling clock edge. It's used in conjunction with VAL_R to determine if the timestamp has been taken\
properly (there was no metastability/setup/hold violation)\
Entries also contain information required to identify the endpoint and frame for which the timestamp was taken:\
- FID - Frame identifier assigned by the NIC\
- PID - TXTSU port ID to which came the timestamp. Used to distinguish the timestamps for broadcast/multicast frames;\
- INCORRECT - timestamp may be incorrect, it has been generated during timebase adjustment";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY};
field {
name = "Rising edge timestamp";
descritpion = "Timestamp value taken on rising clock edge (full word)";
prefix = "val_r";
type = SLV;
size = 28;
};
field {
name = "Falling edge timestamp";
description = "Timestamp value taken on falling clock edge (few LSBs)";
prefix = "val_f";
type = SLV;
size = 4;
};
field {
name ="Physical port ID";
description = "Identifier of the TXTSU port to which came the timestamp. There may be multiple timestamps sharing the same FID value for broadcast/multicast packets.";
prefix = "pid";
type = SLV;
size = 5;
align= 16;
};
field {
name = "Frame ID";
description = "OOB Frame Identifier. Used to associate the timestamp value with transmitted packet.";
prefix = "fid";
type = SLV;
size = 16;
align = 16;
};
field {
name = "Timestamp (possibly) incorrect";
description = "1: This timestamp may be incorrect (generated during PPS adjustment)\
0: Timestamp is correct.";
prefix = "incorrect";
type = BIT;
};
};
-- TXTSU interrupts
irq {
name = "TXTSU fifo not-empty";
description = "Interrupt active when TXTSU shared FIFO contains any timestamps.";
prefix = "nempty";
trigger = LEVEL_1;
};
};
\ No newline at end of file
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment