Commit df504d66 authored by Adam Wujek's avatar Adam Wujek 💬 Committed by Alessandro Rubini

wr_nic: unify nic-hardware.h (spec)

parent 0d82d84c
/*
* hardware-specific definitions for the White Rabbit NIC
*
* Copyright (C) 2010-2012 CERN (www.cern.ch)
* Copyright (C) 2010-2014 CERN (www.cern.ch)
* Author: Alessandro Rubini <rubini@gnudd.com>
*
* This program is free software; you can redistribute it and/or modify
......@@ -10,7 +10,56 @@
*/
#ifndef __WR_NIC_HARDWARE_H__
#define __WR_NIC_HARDWARE_H__
#if (!defined WR_IS_NODE) && (!defined WR_IS_SWITCH)
#error "WR_NODE and WR_SWITCH not defined!"
#endif
#if WR_IS_SWITCH
/* This is the clock used in internal counters. */
#define REFCLK_FREQ (125000000 / 2)
#define NSEC_PER_TICK (NSEC_PER_SEC / REFCLK_FREQ)
/* The interrupt is one of those managed by our WRVIC device */
#define WRN_IRQ_BASE 192
#define WRN_IRQ_NIC (WRN_IRQ_BASE + 0)
#define WRN_IRQ_TSTAMP (WRN_IRQ_BASE + 1)
//#define WRN_IRQ_PPSG (WRN_IRQ_BASE + )
//#define WRN_IRQ_RTU (WRN_IRQ_BASE + )
//#define WRN_IRQ_RTUT (WRN_IRQ_BASE + )
/*
* V3 Memory map, temporarily (Jan 2012)
*
* 0x00000 - 0x1ffff: RT Subsystem
* 0x00000 - 0x0ffff: RT Subsystem Program Memory (16 - 64 kB)
* 0x10000 - 0x100ff: RT Subsystem UART
* 0x10100 - 0x101ff: RT Subsystem SoftPLL-adv
* 0x10200 - 0x102ff: RT Subsystem SPI Master
* 0x10300 - 0x103ff: RT Subsystem GPIO
* 0x10500 - 0x105ff: PPS gen
* 0x20000 - 0x3ffff: NIC
* 0x20000 - 0x20fff NIC control regs and descriptor area
* 0x28000 - 0x2bfff NIC packet buffer (16k)
* 0x30000 - 0x4ffff: Endpoints
* 0x30000 + N * 0x400 Endpoint N control registers
* 0x50000 - 0x50fff: VIC
* 0x51000 - 0x51fff: Tstamp unit
*/
/* This is the base address of all the FPGA regions (EBI1, CS0) */
#define FPGA_BASE_PPSG 0x10010500
#define FPGA_SIZE_PPSG 0x00000100
#define FPGA_BASE_NIC 0x10020000
#define FPGA_SIZE_NIC 0x00010000
#define FPGA_BASE_EP 0x10030000
#define FPGA_SIZE_EP 0x00010000
#define FPGA_SIZE_EACH_EP 0x400
#define FPGA_BASE_VIC 0x10050000 /* not used here */
#define FPGA_SIZE_VIC 0x00001000
#define FPGA_BASE_TS 0x10051000
#define FPGA_SIZE_TS 0x00001000
#endif /* WR_IS_SWITCH */
#if WR_IS_NODE
/* This is the clock used in internal counters. */
#define REFCLK_FREQ (125000000)
#define NSEC_PER_TICK (NSEC_PER_SEC / REFCLK_FREQ)
......@@ -70,6 +119,8 @@
#define FPGA_SIZE_VIC 0x00000100
#define FPGA_BASE_TS 0x00061000
#define FPGA_SIZE_TS 0x0000 100
#endif /* ifdef WR_IS_NODE */
enum fpga_blocks {
WRN_FB_NIC,
......@@ -82,7 +133,8 @@ enum fpga_blocks {
/* In addition to the above enumeration, we scan for those many endpoints */
#if WR_IS_NODE
# define WRN_NR_ENDPOINTS 1
#else
#endif
#if WR_IS_SWITCH
# define WRN_NR_ENDPOINTS 18
#endif
......
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