----------------------------------------------------------------------------------
-- Company: 
-- Engineer: CC
-- 
-- Create Date:    10:03:49 08/07/2015 
-- Design Name: 
-- Module Name:    spi_test master-tx_slave-rx - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity spi_test_mtx_slvrx is
	generic(
		g_period 	: natural := 2500000;	-- period for data Tx
		g_spi_width : natural := 16);			--data spi width
    Port ( clk_i 			: in  STD_LOGIC;
			  rstn_i 		: in  STD_LOGIC;
           data_rx_o 	: out  STD_LOGIC_VECTOR (g_spi_width-1  downto 0);
           data_ready_o : out  STD_LOGIC
           );
end spi_test_mtx_slvrx;

architecture Behavioral of spi_test_mtx_slvrx is

----simple counter to generate data for spi master tx

	COMPONENT counter_tx
	generic(
		g_period 	: integer := 25000;		-- period for data Tx
		g_cnt_width : natural := 16);			--data output width
	PORT(
		clk_i : IN std_logic;
		rstn_i : IN std_logic;          
		data_cnt_o : OUT std_logic_vector(g_cnt_width-1 downto 0);
		data_ready_o : OUT std_logic
		);
	END COMPONENT;

	COMPONENT spi_master
	 Generic (   
      N : positive := 32;                                             -- 32bit serial word length is default
      CPOL : std_logic := '0';                                        -- SPI mode selection (mode 0 default)
      CPHA : std_logic := '0';                                        -- CPOL = clock polarity, CPHA = clock phase.
      PREFETCH : positive := 2;                                       -- prefetch lookahead cycles
      SPI_2X_CLK_DIV : positive := 5); 										 -- for a 100MHz sclk_i, yields a 10MHz SCK
	PORT(
		sclk_i 			: IN std_logic;
		pclk_i 			: IN std_logic;
		rst_i 			: IN std_logic;
		spi_miso_i 		: IN std_logic;
		di_i 				: IN std_logic_vector(N-1 downto 0);
		wren_i 			: IN std_logic;          
		spi_ssel_o 		: OUT std_logic;
		spi_sck_o 		: OUT std_logic;
		spi_mosi_o 		: OUT std_logic;
		di_req_o 		: OUT std_logic;
		wr_ack_o 		: OUT std_logic;
		do_valid_o 		: OUT std_logic;
		do_o 				: OUT std_logic_vector(N-1 downto 0);
		sck_ena_o 		: OUT std_logic;
		sck_ena_ce_o 	: OUT std_logic;
		do_transfer_o 	: OUT std_logic;
		wren_o 			: OUT std_logic;
		rx_bit_reg_o 	: OUT std_logic;
		state_dbg_o 	: OUT std_logic_vector(3 downto 0);
		core_clk_o 		: OUT std_logic;
		core_n_clk_o 	: OUT std_logic;
		core_ce_o 		: OUT std_logic;
		core_n_ce_o 	: OUT std_logic;
		sh_reg_dbg_o 	: OUT std_logic_vector(N-1 downto 0)
		);
	END COMPONENT;	
	
	COMPONENT spi_slave
	Generic (   
	  N : positive := 32;                                             -- 32bit serial word length is default
	  CPOL : std_logic := '0';                                        -- SPI mode selection (mode 0 default)
	  CPHA : std_logic := '0';                                        -- CPOL = clock polarity, CPHA = clock phase.
	  PREFETCH : positive := 3);
	PORT(
		clk_i 			: IN std_logic;
		spi_ssel_i		: IN std_logic;
		spi_sck_i 		: IN std_logic;
		spi_mosi_i 		: IN std_logic;
		di_i 				: IN std_logic_vector(N-1 downto 0);
		wren_i 			: IN std_logic;          
		spi_miso_o 		: OUT std_logic;
		di_req_o 		: OUT std_logic;
		wr_ack_o 		: OUT std_logic;
		do_valid_o 		: OUT std_logic;
		do_o 				: OUT std_logic_vector(N-1 downto 0);
		do_transfer_o 	: OUT std_logic;
		wren_o 			: OUT std_logic;
		rx_bit_next_o 	: OUT std_logic;
		state_dbg_o 	: OUT std_logic_vector(3 downto 0);
		sh_reg_dbg_o 	: OUT std_logic_vector(N-1 downto 0)
		);
	END COMPONENT;

signal data_cnt2m : std_logic_vector(g_spi_width-1 downto 0);	--, data_slvrx
signal data_r2m, data_valid	: std_logic;
signal rstp	: std_logic;		--active high reset
-----spi signals----
signal spi_ssel, spi_sck, spi_mosi : std_logic;


begin

	counter_tx_i: counter_tx 
	generic map(g_period => g_period,
					g_cnt_width => g_spi_width)
	PORT MAP(
		clk_i => clk_i,
		rstn_i => rstn_i,
		data_cnt_o => data_cnt2m,
		data_ready_o => data_r2m
	);

	spi_master_i: spi_master 
	generic map(N => g_spi_width,
					SPI_2X_CLK_DIV => 1)							-- for a 100MHz sclk_i, yields a 50MHz SCK
	PORT MAP(
		sclk_i => clk_i,
		pclk_i => clk_i,
		rst_i => rstp,
		spi_ssel_o => spi_ssel,
		spi_sck_o => spi_sck,
		spi_mosi_o => spi_mosi,
		spi_miso_i => 'X',
		di_req_o => open,
		di_i => data_cnt2m,
		wren_i => data_r2m,
		wr_ack_o => open,
		do_valid_o => open,
		do_o => open,
		sck_ena_o => open,
		sck_ena_ce_o => open,
		do_transfer_o => open,
		wren_o => open,
		rx_bit_reg_o => open,
		state_dbg_o => open,
		core_clk_o => open,
		core_n_clk_o => open,
		core_ce_o => open,
		core_n_ce_o => open,
		sh_reg_dbg_o =>open 
	);

	spi_slave_i: spi_slave 
	generic map(N => g_spi_width)
	PORT MAP(
		clk_i => clk_i,
		spi_ssel_i => spi_ssel,
		spi_sck_i => spi_sck,
		spi_mosi_i => spi_mosi,
		spi_miso_o => open,
		di_req_o => open,
		di_i => (others => 'X'),
		wren_i => 'X',
		wr_ack_o => open,
		do_valid_o => data_ready_o,
		do_o => data_rx_o ,
		do_transfer_o => open,
		wren_o => open,
		rx_bit_next_o => open,
		state_dbg_o => open,
		sh_reg_dbg_o => open
	);

	rstp <= not rstn_i;  --active high reset

end Behavioral;
