----------------------------------------------------------------------------------
-- Company: 
-- Engineer: CC
-- 
-- Create Date:    16:06:08 10/02/2017
-- Design Name: 
-- Module Name:    time_out_gen - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity time_out_gen is

	generic(
		 g_timeout_val : natural := 65500 --	~100ms @ 62.5MHz
		 );
    Port (
		clk_i				: in std_logic;
		rst_i				: in std_logic;
		timeout_en_i 	: in std_logic;
		timeout_hit_o	: out std_logic
	 );
end time_out_gen;

architecture Behavioral of time_out_gen is

--	signal timeout_counter 	: unsigned(9 downto 0);	
	signal timeout_counter 	: natural := 0;	
	
begin

	
p_timeout_cnt : process(clk_i)
  begin
    if rising_edge(clk_i) then
      if rst_i = '1' then
        timeout_counter <= 0;				-- (others => '0');      
		elsif timeout_en_i = '1' then
          timeout_counter <= timeout_counter + 1;      
		else
			timeout_counter <= 0;				-- (others => '0');
       end if;
    end if;
  end process;

p_timeout: process(clk_i)
  begin
    if rising_edge(clk_i) then
      if rst_i = '1' then
        timeout_hit_o <= '0';
	  elsif(timeout_counter = g_timeout_val -1) then
			timeout_hit_o <= '1';
	  else
			timeout_hit_o <= '0';
      end if;
    end if;
  end process;
	
end Behavioral;
