----------------------------------------------------------------------------------
-- Company: 
-- Engineer: CC
-- 
-- Create Date:    16:06:08 16/09/2015
-- Design Name: 
-- Module Name:    pps_counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: pps counter and separate pps detect
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Revision 0.02 - reset '1' Xilinx prefered
-- Revision 0.03 - single clock cycle PPS, no more need for PPS detection
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity pps_counter is

    Port (
		clk_i				: in std_logic;
		rst_i			: in std_logic;
		pps_i 			: in std_logic;
		--pps_detect_o	: out std_logic;
		pps_cnt_o		: out std_logic_vector(15 downto 0) -- 16bits => 12h 
	 );
end pps_counter;

architecture Behavioral of pps_counter is

	signal pps_cnt 		: unsigned(15 downto 0) := (others =>'0');
	--signal pps_detect 	: std_logic_vector(1 downto 0):= "11";
	
--	attribute ASYNC_REG: string;
--	attribute ASYNC_REG of pps_detect(0)	: label is "TRUE";
--	attribute ASYNC_REG of pps_detect(1)	: label is "TRUE";
	
	
begin
	pps_counter_proc :PROCESS (clk_i)
       BEGIN	  		
			if rising_edge(clk_i)  then
				if (rst_i = '1') then
					pps_cnt <= (others =>'0');
				elsif (pps_i = '1') then  				-- PPS rising edge	
					pps_cnt 	<=  pps_cnt + 1;
				end if;
			end if;
  end process;	
  
--  pps_detect_proc : PROCESS (clk_i)
--       BEGIN	  
--			if rising_edge(clk_i)  then
--				pps_detect(0) 		<= pps_i;
--				pps_detect(1)		<= pps_detect(0);
--				if (pps_detect = "01") then  				-- PPS rising edge	
--					pps_detect_o <= '1';
--				else 
--					pps_detect_o <= '0';
--				end if;
--			end if;
--  end process;	
  
	pps_cnt_o 	<= std_logic_vector(pps_cnt);	
	

	
end Behavioral;
