----------------------------------------------------------------------------------
-- Company: 
-- Engineer: CC
-- 
-- Create Date:    11:06:08 23/12/2016
-- Design Name: 
-- Module Name:    ext_trig_gen - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: generate a trigger to camera at a date received through UDP
--
-- Dependencies: 
--
-- Revision 0.01 - File Created
-- Additional Comments: 
-- 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity  ext_trig_gen is

    Port (
		clk_i					: in std_logic;
		clk_ref_i			: in std_logic;		--125MHz
		rst_i					: in std_logic;
		ext_trig_en_i		: in std_logic;
		tm_seconds_i 		: in std_logic_vector(24 downto 0);
		tm_cycles_i 		: in std_logic_vector(27 downto 0);
		ext_trig_date_i 	: in std_logic_vector(52 downto 0);
		ext_trig_o			: out std_logic := '0'
--		TRIG3					: out std_logic_vector(31 downto 0)
	 );
end  ext_trig_gen;

architecture Behavioral of ext_trig_gen is

	component gc_extend_pulse is
	  generic (
		 -- output pulse width in clk_i cycles
		 g_width : natural := 1000
		 );
	  port (
		 clk_i      : in  std_logic;
		 rst_n_i    : in  std_logic;
		 -- input pulse (synchronou to clk_i)
		 pulse_i    : in  std_logic;
		 -- extended output pulse
		 extended_o : out std_logic
		 );
	end component;

	signal cntdown 			: unsigned(27 downto 0) := (others =>'0');
	signal date_seconds 		: std_logic_vector(24 downto 0):= (others =>'0');
	signal date_8ns	 		: unsigned(27 downto 0):= (others =>'0');
	signal trig_date_valid, ext_trig  : std_logic := '0';
	 
begin


 PROCESS (clk_i)
       BEGIN	  
			
			if rising_edge(clk_i)  then
				if (rst_i = '1') then
					date_8ns 	 	 <= (others =>'0');
					date_seconds 	 <= (others =>'0');
					trig_date_valid <= '0';
				elsif (ext_trig_en_i = '1') then  
					date_8ns		 	 <= unsigned(ext_trig_date_i(27 downto 0));
					date_seconds 	 <= ext_trig_date_i(52 downto 28);
					trig_date_valid <= '1';
				else
					trig_date_valid <= '0';
				end if;
			end if;
  end process;
  
	
 PROCESS (clk_ref_i)
       BEGIN	  
			
			if rising_edge(clk_ref_i)  then
				if trig_date_valid = '1' then
					cntdown 	<= date_8ns;
				elsif date_seconds = tm_seconds_i then
					if cntdown = x"0000000"then
						ext_trig 	<= '1';
						cntdown 		<= (others => '1');
					elsif cntdown = x"0000001" then
						ext_trig 	<= '1';			-- width = one clock cycle, 8ns enough ?
						cntdown 		<= (others => '1');
					else cntdown <=  cntdown - 1;
						ext_trig <= '0';
					end if;
				end if;
			end if;
  end process;	

--  -- wider pulse---
U_Extend_Pulse : gc_extend_pulse
    generic map ( g_width => 5)
    port map (
      clk_i      => clk_ref_i,
      rst_n_i    => not rst_i,
      pulse_i    => ext_trig,
      extended_o => ext_trig_o
		);  
 
--TRIG3(27 downto 0) <= std_logic_vector(cntdown);
--TRIG3(28) 			 <= trig_date_valid;
--TRIG3(29) 			 <= ext_trig;
--  
  
end Behavioral;
