-- TestBench Template 

  LIBRARY ieee;
  USE ieee.std_logic_1164.ALL;
  USE ieee.numeric_std.ALL;
  
  -- UDP/IP library
	use work.data_IO.all;
	use work.ipv4_types.all;

	--WR library
	use work.wr_fabric_pkg.all;
	use work.genram_pkg.all;

  ENTITY udp_top_tb IS
  END udp_top_tb;

  ARCHITECTURE behavior OF udp_top_tb IS 

  -- Component Declaration
   COMPONENT udp_top
          generic( 
				g_data_tx_width  		: natural := 16;
				g_add_data_tx_width 	: natural := 16;
				g_nb_data_packed 		: natural := 20;
				g_data_rx_width  		: natural := 16
				);
    Port ( 
			clk_sys_i : in std_logic;
			rst_n_i   : in std_logic;
					
      -- Endpoint/WRC interface - packet source
			src_i : in  t_wrf_source_in;
			src_o : out t_wrf_source_out;
			
		-- Endpoint/WRC interface - packet sink
			snk_i : in  t_wrf_sink_in;
			snk_o : out t_wrf_sink_out;
			
    ---------------------------------------------------------------------------
    -- User interface
    ---------------------------------------------------------------------------
		-----TX
		 -- Data word to be sent. 
         tx_data_i 			: in  STD_LOGIC_VECTOR (g_data_tx_width-1 downto 0);
		 -- 1 indicates that the tx_data_i contains a valid data word.
         tx_data_ready_i 	: in  STD_LOGIC;
		--additionnal information sent once with bunch
			add_tx_data_i		: in  STD_LOGIC_VECTOR (g_add_data_tx_width-1 downto 0);			
			
		----RX
		-- Data word received. 
         rx_data_o 			: out  STD_LOGIC_VECTOR (g_data_rx_width-1 downto 0);
		 -- 1 indicates that the rx_data_o contains a valid data word.
         rx_data_ready_o 	: out  STD_LOGIC;

			---------------------------------------------------------------------------
    -- Configuration
    ---------------------------------------------------------------------------

		-- Local MAC address. Leave at 0 when using with the WR MAC/Core, it will
		-- insert its own source MAC.
			cfg_mac_local_i : in std_logic_vector(47 downto 0) := x"000000000000";
		-- Destination MAC address.
			cfg_mac_target_i : in std_logic_vector(47 downto 0);
		--IP address. .
			cfg_ip_local_i  : in std_logic_vector(31 downto 0) := x"C0A80064"; 			--IP src 192.168.0.100
			cfg_ip_target_i : in std_logic_vector(31 downto 0) := x"C0A8000A";  		--IP dst 192.168.0.10		 
		--Port
			cfg_port_i : in std_logic_vector (15 downto 0)  := x"D6D8";	--port 55000
			
			-- Tx FIFO signals
			reset_fifo_i		: in std_logic;
			tx_almost_empty_o	: out  STD_LOGIC;
			tx_almost_full_o  	: out  STD_LOGIC
		);
        END COMPONENT;
		
		signal clk_sys_i :  std_logic;
		signal rst_n_i   :  std_logic := '1';
					
      -- Endpoint/WRC interface - packet source
		signal	src_i : t_wrf_source_in;
		signal	src_o : t_wrf_source_out;
			
		-- Endpoint/WRC interface - packet sink
		signal	snk_i : t_wrf_sink_in;
		signal	snk_o : t_wrf_sink_out;
     ---------------------------------------------------------------------------
    -- User interface
    ---------------------------------------------------------------------------
		-----TX
		 -- Data word to be sent. 
      signal tx_data_i 	: STD_LOGIC_VECTOR (95 downto 0) :=(others => '0');
		 -- 1 indicates that the tx_data_i contains a valid data word.
      signal tx_data_ready_i : STD_LOGIC := '0';
		--additionnal information sent once with bunch
		signal add_tx_data_i	: STD_LOGIC_VECTOR (127 downto 0) :=(others => '0');			
			
		----RX
		-- Data word received. 
       signal rx_data_o 	: STD_LOGIC_VECTOR (63 downto 0) :=(others => '0');
		 -- 1 indicates that the rx_data_o contains a valid data word.
       signal rx_data_ready_o : STD_LOGIC :='0';

	---------------------------------------------------------------------------
    -- Configuration
    ---------------------------------------------------------------------------

		-- Local MAC address. Leave at 0 when using with the WR MAC/Core, it will
		-- insert its own source MAC.
		signal cfg_mac_local_i  : std_logic_vector(47 downto 0) := x"BBBBBBBBBBBB";
		-- Destination MAC address.
		signal cfg_mac_target_i : std_logic_vector(47 downto 0) := x"AAAAAAAAAAAA";
		--IP address. .
		signal cfg_ip_local_i : std_logic_vector(31 downto 0) := x"C0A80064"; 			--IP src 192.168.0.100
		signal cfg_ip_target_i :  std_logic_vector(31 downto 0) := x"C0A8000A";  		--IP dst 192.168.0.10		 
		--Port
		signal cfg_port_i : std_logic_vector (15 downto 0)  := x"D6D8";	--port 55000
			
			-- Tx FIFO signals
		signal reset_fifo_i : std_logic;
		signal tx_almost_empty_o :  STD_LOGIC := '0';
		signal tx_almost_full_o  :  STD_LOGIC := '0';    
	
	-- Clock period definitions
		constant clk_i_period : time := 16 ns;
		
		signal tx_data : integer := 0;
	
  BEGIN

  -- Component Instantiation
   uut: udp_top 
  generic map( g_data_tx_width  		=> 96,	--number of bits 128,
					g_add_data_tx_width 	=> 128,   --number of bits 80,
					g_data_rx_width 		=> 64,	--number of bits
					g_nb_data_packed 		=> 24		--number of data packets in one UDP frame
					)		
  port map (
		clk_sys_i 			=> clk_sys_i,
		rst_n_i 				=> rst_n_i,				
		tx_data_i 			=> tx_data_i,
      tx_data_ready_i	=> tx_data_ready_i,			-- and (not stop_wr_fifo),				---tx_tag_valid,	
      reset_fifo_i		=> reset_fifo_i,
		add_tx_data_i		=> add_tx_data_i, 			--additionnal information sent once with bunch
		rx_data_o 			=> rx_data_o,
		rx_data_ready_o	=> rx_data_ready_o,
		src_i 				=> src_i,				
		src_o 				=> src_o ,			
		snk_i 				=> snk_i,				
		snk_o 				=> snk_o,			
		cfg_mac_local_i 	=> x"000000000000",			
		cfg_mac_target_i	=> cfg_mac_target_i,			
		cfg_ip_local_i 	=> cfg_ip_local_i,				
		cfg_ip_target_i 	=>	cfg_ip_target_i,					
		cfg_port_i 			=>	cfg_port_i						--port 55000	x"D6D8"	
	);


	-- Clock process definitions
   clk_i_process :process
   begin
		clk_sys_i <= '0';
		wait for clk_i_period/2;
		clk_sys_i <= '1';
		wait for clk_i_period/2;
   end process;

		--  reset
     reset_proc : PROCESS
     BEGIN
			rst_n_i <= '0';
        wait for 100 ns; -- wait until global set/reset completes
			rst_n_i <= '1';
		  wait ; 
	    END PROCESS reset_proc;
  --  End reset

	tx_data_i 		<= std_logic_vector(to_unsigned(tx_data,96));
	add_tx_data_i 	<= std_logic_vector(to_unsigned(tx_data,128));
	
  --  Test Bench Statements
     tb : PROCESS
     BEGIN
			tx_data_ready_i 	<= '0';
		   wait for 850 ns; 
			tx_data_ready_i 	<= '1';
			tx_data 		 		<= tx_data + 1;
			wait for clk_i_period;
			tx_data_ready_i 	<= '0';
			tx_data		 		<= tx_data ;
			wait for 1030 ns; 
     END PROCESS tb;
  --  End Test Bench 

  END;
