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-- Company: 
-- Engineer:
--
-- Create Date:   11:03:54 08/07/2015
-- Design Name:   
-- Module Name:   /home/cchamp/Xilinx/spi_master_slave/trunk/spi_slave/spi_tb.vhd
-- Project Name:  spi_slave
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: spi_test_mtx_slvrx
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY spi_tb IS
END spi_tb;
 
ARCHITECTURE behavior OF spi_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT spi_test_mtx_slvrx
    PORT(
         clk_i : IN  std_logic;
         rstn_i : IN  std_logic;
         data_rx_o : OUT  std_logic_vector(31 downto 0);
         data_ready_o : OUT  std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk_i : std_logic := '0';
   signal rstn_i : std_logic := '0';

 	--Outputs
   signal data_rx_o : std_logic_vector(31 downto 0) :=(others => '0');
   signal data_ready_o : std_logic;

   -- Clock period definitions
   constant clk_i_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: spi_test_mtx_slvrx PORT MAP (
          clk_i => clk_i,
          rstn_i => rstn_i,
          data_rx_o => data_rx_o,
          data_ready_o => data_ready_o
        );

   -- Clock process definitions
   clk_i_process :process
   begin
		clk_i <= '0';
		wait for clk_i_period/2;
		clk_i <= '1';
		wait for clk_i_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		rstn_i <= '0';
      wait for clk_i_period*10;
		rstn_i <= '1';
      -- insert stimulus here 

      wait;
   end process;

END;
