----------------------------------------------------------------------------------
-- Company: CNRS
-- Engineer: CC
-- 
-- Create Date:    14:58:08 09/03/2015 
-- Design Name: 
-- Module Name:    ascii_conv - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.ipv4_types.all;
use IEEE.NUMERIC_STD.ALL;


entity ascii_conv is
	generic(
     g_data_width  	: natural := 16;
	 g_padding_length : natural := 32 );	---padding 64 bytes
    Port ( 
		   rstn_i 					: in  STD_LOGIC;
           clk_i 					: in  STD_LOGIC;
           udp_rx_data_ready_i		: in  STD_LOGIC;
           udp_rx_data_i 			: in  STD_LOGIC_VECTOR (g_data_width-1 downto 0);
           rx_data_o 				: out  STD_LOGIC_VECTOR ((g_data_width-1)/8) downto 0);
           data_valid_o 			: out  STD_LOGIC);
end ascii_conv;

architecture Behavioral of ascii_conv is

	TYPE STATE_TYPE IS (
			IDLE, 			-- initial state - wait ou Init
			CONV,			-- convert ASCII data to bit
			DATA_OUT 		-- 
		);
		
	signal current_state : STATE_TYPE ;
	
	signal data_valid 	: STD_LOGIC;
	signal buffer_rx 	: std_logic_vector (g_data_width-1 downto 0); --data 1 byte received = 1 bit
	signal rx_count     : unsigned (15 downto 0);
	 
begin
	-- Process MAE
   PROCESS(clk_i, rstn_i)		  
   BEGIN
	
	IF (rstn_i = '0') THEN
		buffer_Rx 	<= (others=> '0');
		data_valid 	<= '0';
		rx_count    <= (others => '0');		
		current_state <= IDLE; 
		
	ELSIF rising_edge(clk_i) THEN
		CASE current_state IS 
	
			WHEN IDLE =>
				data_valid  <= '0';
				buffer_Rx 	<= (others=> '0');	
				rx_count    <= (others => '0');
					if (udp_rx_data_ready_i = '1') then
						buffer_rx <= udp_rx_data_i ; 							-- 1 word 16bits received = 2 bits data 
						current_state <= CONV;
					else 
						current_state <= IDLE; 
					end if;																	
				end if;
				
				WHEN	CONV =>
				if (buffer_rx (15 downto 8) = x"31)" then
					rx_data_o(1) <='1';
					else rx_data_o(1) <='0';
				end if;
				if (buffer_rx (7 downto 0) = x"31)" then
					rx_data_o(0) <='1';
					else rx_data_o() <='0';
				end if;
							
				
	
				
--			WHEN	RX =>
--				data_valid <= '0';
--				buffer_rx(1 downto 0) <= udp_rx_i.data.data_in(8) & udp_rx_i.data.data_in(0);
----				if (udp_rx_i.data.data_in_valid = '1') then
----					buffer_rx(g_data_width-1 downto 2)  <= buffer_rx( g_data_width-3 downto 0);
------					buffer_rx(0)  <= udp_rx_i.data.data_in(0);
----					--buffer_rx(1) <= udp_rx_i.data.data_in(8); 					
----				end if;
--				
--				if (udp_rx_i.data.data_in_last = '1') then
--					current_state <= DATA_OUT;
--				else 
----					buffer_rx(1 downto 0) <= udp_rx_i.data.data_in(8) & udp_rx_i.data.data_in(0);
--					buffer_rx(g_data_width-1 downto 2)  <= buffer_rx( g_data_width-3 downto 0);
--					current_state <= RX;
--				end if;
				
			WHEN	DATA_OUT => 
--				udp_rx_data_o <= buffer_rx;
				buffer_rx <= buffer_rx;
				data_valid 		<= '1';
				rx_count <= (others=> '0');
				current_state <= IDLE;

			WHEN OTHERS =>
				current_state <= IDLE;

			END CASE;	
		end if;
	END PROCESS;

data_valid_o <= data_valid;
udp_rx_data_o <= buffer_rx;

end Behavioral;


