----------------------------------------------------------------------------------
-- Company: 
-- Engineer: CC
-- 
-- Create Date:    16:02:55 04/16/2015 
-- Design Name: 
-- Module Name:    counter_tx - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: Simple counter to test ethernet TX
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity counter_tx is
generic(
	 g_period 		: natural := 2500000;	-- period for data Tx
    g_cnt_width   : natural := 16);
    Port ( clk_i 			: in  STD_LOGIC;   -- 62.5 MHz
           rstn_i 		: in  STD_LOGIC;
           data_cnt_o 	: out STD_LOGIC_VECTOR (g_cnt_width-1 downto 0);
           data_ready_o : out STD_LOGIC
           );
end counter_tx;

architecture Behavioral of counter_tx is

signal cnt_val  	: integer := 0;
signal cnt_val2  	: integer := 0;
signal cnt2_inc, data_ready, data_ready2	: STD_LOGIC ;

begin

	--clock div process
	clk_div_proc:process(clk_i,rstn_i)is	
	begin	
	if rising_edge(clk_i) then		
		if (rstn_i = '0') then
		cnt_val 		<= 0; 
		cnt2_inc  	<= '0' ;
		else	
			if (cnt_val = g_period-1) then
			 cnt_val  	<= 0 ;
			 cnt2_inc	<= '1';
			else 
			 cnt_val  	<= cnt_val + 1;
			 cnt2_inc  	<= '0' ;
			end if;
		end if;
	end if;	
	end process clk_div_proc;
	
	--counter process
	cnt_proc:process(clk_i, rstn_i)is	
	begin
	if rising_edge(clk_i) then	
		if (rstn_i = '0') then
		 cnt_val2 	 <= 0; 
		 data_ready <= '0';
		elsif (cnt2_inc ='1') then
		 cnt_val2  	 <= cnt_val2 + 1;
		 data_ready <= '1';
		else
		 cnt_val2  	 <= cnt_val2;
		 data_ready <= '0';
		end if;
	end if;
	end process cnt_proc;
	
	
  data_cnt_o    	<= std_logic_vector(to_unsigned(cnt_val2,g_cnt_width)); 
  data_ready_o 	<= data_ready;

end Behavioral;

