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-- Company: 
-- Engineer:
--
-- Create Date:   17:01:44 03/01/2017
-- Design Name:   
-- Module Name:   /home/cchamp/Xilinx/14.7/ISE/wr-coresv3/ucts_git/modules/clock/event_cnt_tb.vhd
-- Project Name:  ucts_top_wrc
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: event_counter
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY event_cnt_tb IS
END event_cnt_tb;
 
ARCHITECTURE behavior OF event_cnt_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT event_counter
    PORT(
         clk_i : IN  std_logic;
         rst_i : IN  std_logic;
         event_i : IN  std_logic;
         event_cnt_o : OUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk_i : std_logic := '0';
   signal rst_i : std_logic := '0';
   signal event_i : std_logic := '0';

 	--Outputs
   signal event_cnt_o : std_logic_vector(31 downto 0);

   -- Clock period definitions
   constant clk_i_period : time := 16 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: event_counter 
	PORT MAP (
          clk_i => clk_i,
          rst_i => rst_i,
          event_i => event_i,
          event_cnt_o => event_cnt_o
        );

   -- Clock process definitions
   clk_i_process :process
   begin
		clk_i <= '0';
		wait for clk_i_period/2;
		clk_i <= '1';
		wait for clk_i_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		rst_i	<= '1';
      wait for clk_i_period*10;	
		rst_i	<= '0';
		wait for clk_i_period*20;
      -- insert stimulus here 
		event_i <= '1';
		wait for clk_i_period*10;
		event_i <= '0';
		wait for clk_i_period*20;
		event_i <= '1';
		wait for clk_i_period*10;
		event_i <= '0';
		wait for 100 ns;	
		rst_i	<= '1';
      wait for clk_i_period*10;	
		rst_i	<= '0';
		wait for clk_i_period*20;
		event_i <= '1';
		wait for clk_i_period*10;
		event_i <= '0';
      wait;
   end process;

END;
