#bank 0
NET "CLK_20M_VCXO_I" LOC = H12;
NET "CLK_20M_VCXO_I" IOSTANDARD = "LVCMOS25";

NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";

NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";

NET "fpga_pll_ref_clk_101_n_i" LOC = D11;
NET "fpga_pll_ref_clk_101_n_i" IOSTANDARD = "LVDS_25";

NET "fpga_pll_ref_clk_101_p_i" LOC = C11;
NET "fpga_pll_ref_clk_101_p_i" IOSTANDARD = "LVDS_25";


NET "dac_cs1_n_o" LOC = A3;
NET "dac_cs1_n_o" IOSTANDARD = "LVCMOS25";

NET "dac_cs2_n_o" LOC = B3;
NET "dac_cs2_n_o" IOSTANDARD = "LVCMOS25";

#NET "dac_clr_n_o" LOC = F7;
#NET "dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "dac_din_o" LOC = C4;
NET "dac_din_o" IOSTANDARD = "LVCMOS25";

NET "dac_sclk_o" LOC = A4;
NET "dac_sclk_o" IOSTANDARD = "LVCMOS25";

#NET "SI57X_CLK_N" LOC = F15;
#NET "SI57X_CLK_N" IOSTANDARD = "LVDS_25";
#NET "SI57X_CLK_P" LOC = F14;
#NET "SI57X_CLK_P" IOSTANDARD = "LVDS_25";
#NET "TCK_TO_FMC" LOC = G8;
#NET "TCK_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TDI_TO_FMC" LOC = H11;
#NET "TDI_TO_FMC" IOSTANDARD = "LVCMOS25";
NET "thermo_id" LOC = D4;
NET "thermo_id" IOSTANDARD = "LVCMOS25";
#NET "TMS_TO_FMC" LOC = H10;
#NET "TMS_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "PRSNT_M2C_L" LOC = A2;
#NET "PRSNT_M2C_L" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF1_b" LOC = C17;
NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_b" LOC = G15;
NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF2_b" LOC = G16;
NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
NET "SFP_RATE_SELECT_b" LOC = H14;
NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_FAULT_i" LOC = A17;
NET "SFP_TX_FAULT_i" LOC = B18;
NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_DISABLE_o" LOC = F17;
NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
NET "SFP_LOS_i" LOC = D18;
NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";

#NET "sfp_rxp_i" IOSTANDARD = "LVDS_12";
NET "sfp_rxp_i" LOC= D15;
#NET "sfp_rxn_i" IOSTANDARD = "LVDS_12";
NET "sfp_rxn_i" LOC= C15;

#NET "sfp_txp_o" IOSTANDARD = "LVDS_12";
NET "sfp_txp_o" LOC= B16;
#NET "sfp_txn_o" IOSTANDARD = "LVDS_12";
NET "sfp_txn_o" LOC= A16;


#NET "TRST_TO_FMC" LOC = E6;
#NET "TRST_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "CLK0_M2C_P" LOC = E16;
#NET "CLK0_M2C_P" IOSTANDARD = "LVDS_25";
NET "FPGA_SCL_B" LOC = F7;
NET "FPGA_SCL_B" IOSTANDARD = "LVCMOS25";
NET "FPGA_SDA_B" LOC = F8;
NET "FPGA_SDA_B" IOSTANDARD = "LVCMOS25";

NET "SPI_NCS_O"  LOC = AA3;
NET "SPI_NCS_O"  IOSTANDARD = "LVCMOS25";
NET "SPI_SCLK_O" LOC = Y20;
NET "SPI_SCLK_O"  IOSTANDARD = "LVCMOS25";
NET "SPI_MOSI_O" LOC = AB20;
NET "SPI_MOSI_O"  IOSTANDARD = "LVCMOS25";
NET "SPI_MISO_I" LOC = AA20;
NET "SPI_MISO_I"  IOSTANDARD = "LVCMOS25";


NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";

#NET "PCB_VER[0]" LOC = P5;
#NET "PCB_VER[0]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[1]" LOC = P4;
#NET "PCB_VER[1]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[2]" LOC = AA2;
#NET "PCB_VER[2]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[3]" LOC = AA1;
#NET "PCB_VER[3]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[4]" LOC = N6;
#NET "PCB_VER[4]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[5]" LOC = N7;
#NET "PCB_VER[5]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[6]" LOC = U4;
#NET "PCB_VER[6]" IOSTANDARD = "LVCMOS15";
#NET "PCB_VER[7]" LOC = T4;
#NET "PCB_VER[7]" IOSTANDARD = "LVCMOS15";

#########################################################
###  Pin definitions for RJ45 FMC board + TiCkSv4.1  ##
#########################################################
## outputs
####clk_sync
#BANK0
NET "clk_sync_p_o" LOC= E16;
NET "clk_sync_p_o" IOSTANDARD=LVDS_25;
NET "clk_sync_n_o" LOC= F16;
NET "clk_sync_n_o" IOSTANDARD=LVDS_25;

####PPS
#BANK2
NET "pps_p_o" LOC= T8;
NET "pps_p_o" IOSTANDARD=LVDS_25;
NET "pps_n_o" LOC= U8;
NET "pps_n_o" IOSTANDARD=LVDS_25;

#calibration PPS
#NET "pps_cal_p_o" LOC= AA4;
#NET "pps_cal_p_o" IOSTANDARD=LVDS_25;
#NET "pps_cal_n_o" LOC= AB4;
#NET "pps_cal_n_o" IOSTANDARD=LVDS_25;
#####ext_trig
#BANK2
NET "ext_trig_p_o" LOC= V11;
NET "ext_trig_p_o" IOSTANDARD=LVDS_25;
NET "ext_trig_n_o" LOC= W11;
NET "ext_trig_n_o" IOSTANDARD=LVDS_25;

## inputs
#BANK2
NET "spi_data_p_i" LOC= R11;
NET "spi_data_p_i" IOSTANDARD=LVDS_25;
NET "spi_data_n_i" LOC= T11;
NET "spi_data_n_i" IOSTANDARD=LVDS_25;

#BANK2
NET "spi_ssel_p_i" LOC= T15;
NET "spi_ssel_p_i" IOSTANDARD=LVDS_25;
NET "spi_ssel_n_i" LOC= U15;
NET "spi_ssel_n_i" IOSTANDARD=LVDS_25;

#BANK2		
NET "spi_clk_p_i" LOC= T12;
NET "spi_clk_p_i" IOSTANDARD=LVDS_25;
NET "spi_clk_n_i" LOC= U12;
NET "spi_clk_n_i" IOSTANDARD=LVDS_25;


###busy_trig
#BANK2				TiCkS
NET "busy_trig_p_i" LOC= Y7;
NET "busy_trig_p_i" IOSTANDARD=LVDS_25;
#NET "busy_trig_p_i" PULLDOWN;
NET "busy_trig_n_i" LOC= AB7;
#NET "busy_trig_n_i" PULLUP;
NET "busy_trig_n_i" IOSTANDARD=LVDS_25;
####event_trig
#BANK2
NET "event_trig_p_i" LOC= U9;
NET "event_trig_p_i" IOSTANDARD=LVDS_25;
#NET "event_trig_p_i" PULLDOWN;
NET "event_trig_n_i" LOC= V9;
#NET "event_trig_n_i" PULLUP;
NET "event_trig_n_i" IOSTANDARD=LVDS_25;
###UART
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD=LVCMOS25;
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD=LVCMOS25;


#---------------------------------------------------------------------------------------------
# False Path
#---------------------------------------------------------------------------------------------
NET "clk_20m_vcxo_i" TNM_NET = clk_20m_vcxo_i;
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "fpga_pll_ref_clk_101_p_i" TNM_NET = fpga_pll_ref_clk_101_p_i;
TIMESPEC TS_fpga_pll_ref_clk_101_p_i = PERIOD "fpga_pll_ref_clk_101_p_i" 8 ns HIGH 50%;
NET "fpga_pll_ref_clk_101_n_i" TNM_NET = fpga_pll_ref_clk_101_n_i;
TIMESPEC TS_fpga_pll_ref_clk_101_n_i = PERIOD "fpga_pll_ref_clk_101_n_i" 8 ns HIGH 50%;

#PIN "clk_125m_pllref_BUFG.O" CLOCK_DEDICATED_ROUTE = FALSE; 
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/06/09
NET "U_GTP/ch1_gtp_clkout_int<1>" TNM_NET = U_GTP/ch1_gtp_clkout_int<1>;
TIMESPEC TS_U_GTP_ch1_gtp_clkout_int_1_ = PERIOD "U_GTP/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; 
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;

TIMESPEC TS_ = FROM "skew_limit" TO "FFS" 1 ns DATAPATHONLY;


NET "clk_125m_pllref_p_i" CLOCK_DEDICATED_ROUTE = FALSE;
NET "clk_125m_pllref_n_i" CLOCK_DEDICATED_ROUTE = FALSE;
##Clock output 10MHz
#TIMESPEC TS_clk_sync_n_o = PERIOD "clk_sync_n_o" 100 ns HIGH 50%;
#NET "clk_sync_n_o" TNM_NET = clk_sync_n_o;
#TIMESPEC TS_clk_sync_p_o = PERIOD "clk_sync_p_o" 100 ns HIGH 50%;
#NET "clk_sync_p_o" TNM_NET = clk_sync_p_o;
#---------------------------------------------------------------------------------------------
# Register output PPS signal. Minimize the delay from register to pad.
#INST "U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB =FORCE;
#
#INST "*/U_Wrapped_Endpoint/U_PCS_1000BASEX/gen_8bit.U_RX_PCS/timestamp_trigger_p_a_o" TNM = "rx_ts_trig";
#TIMESPEC TS_RXTS = FROM "rx_ts_trig" TO  FFS 1 ns DATAPATHONLY;
#
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" BEL = D5FF;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in" LOC = SLICE_X30Y64;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in_INV*" BEL = D6LUT;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in_INV*" LOC = SLICE_X31Y64;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in_INV*" BEL = D6LUT;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_in_INV*" LOC = SLICE_X30Y64;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" BEL = D5FF;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_in" LOC = SLICE_X31Y64;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d0" BEL = AFF;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d0" LOC = SLICE_X30Y65;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d1" BEL = BFF;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d1" LOC = SLICE_X30Y65;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d2" BEL = CFF;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d2" LOC = SLICE_X30Y65;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" BEL = DFF;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d3" LOC = SLICE_X30Y65;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0" BEL = AFF;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d0" LOC = SLICE_X31Y65;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d1" BEL = BFF;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d1" LOC = SLICE_X31Y65;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d2" BEL = CFF;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d2" LOC = SLICE_X31Y65;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" BEL = DFF;
#INST "U_WR_CORE/WRPC/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds[0].DMTD_REF/clk_i_d3" LOC = SLICE_X31Y65;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/03/20
#NET "clk_sync_n_o" OFFSET = OUT 8 ns AFTER "clk_125m_pllref_n_i" REFERENCE_PIN "pps_n_o";
#NET "clk_sync_p_o" OFFSET = OUT 8 ns AFTER "clk_125m_pllref_n_i" REFERENCE_PIN "pps_p_o";
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/03/20
#NET "pps_cal_n_o" OFFSET = OUT 8 ns AFTER "clk_125m_pllref_n_i" REFERENCE_PIN "pps_n_o";
#NET "pps_cal_p_o" OFFSET = OUT 8 ns AFTER "clk_125m_pllref_n_i" REFERENCE_PIN "pps_p_o";
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/03/21
#INST "U_WR_CORE/WRPC/PPS_GEN/WRAPPED_PPSGEN/pps_out_o" IOB = TRUE;
#NET "clk_125m_pllref_p_i" FEEDBACK = 20 ns NET "clk_sync_p_o";
#NET "clk_125m_pllref_n_i" FEEDBACK = 20 ns NET "clk_sync_n_o";
#NET "clk_125m_pllref_p_i" FEEDBACK = 20 ns NET "pps_p_o";
#NET "clk_125m_pllref_n_i" FEEDBACK = 20 ns NET "pps_n_o";
