----------------------------------------------------------------------------------
-- Company: 
-- Engineer: CC
-- 
-- Create Date:    16:26:08 16/04/2017
-- Design Name: 
-- Module Name:    clk_counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision 0.01 - File Created
-- Revision 0.02 - 28 bits counter 268MHz max
-- Additional Comments: 
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity clk_counter is

    Port (
		clk_i				: in std_logic;
		pps_i				: in std_logic;
--		rst_i				: in std_logic;
		event_i 			: in std_logic;
		event_cnt_o		: out std_logic_vector(25 downto 0) 
	 );
end clk_counter;

architecture Behavioral of clk_counter is

	signal event_cnt 	: unsigned(25 downto 0) := (others =>'0');
	signal pps_detect : std_logic_vector(1 downto 0):= "11";
 
begin

	event_cnt_o 	<= std_logic_vector(event_cnt);	
	
cnt_proc: PROCESS (clk_i)
       BEGIN	  
			if rising_edge(clk_i)  then
				if (pps_detect = "01") then  				-- PPS rising edge
					event_cnt 	<= (others =>'0');
				else					
					event_cnt 	<=  event_cnt + 1;
				end if;
			end if;
  end process;			
	
 pps_detect_proc : PROCESS (clk_i)
       BEGIN	  
			if rising_edge(clk_i)  then
				pps_detect(0) 		<= pps_i;
				pps_detect(1)		<= pps_detect(0);
			end if;
  end process;
  
  
--cnt_proc: PROCESS (clk_i)
--       BEGIN	  
--			if (rst_i = '1') then
--					event_cnt 	<= (others =>'0');
--			elsif rising_edge(clk_i)  then
----				if (rst_i = '1') then
----					event_cnt 	<= (others =>'0');
----				else					
--					event_cnt 	<=  event_cnt + 1;
----				end if;
--			end if;
--  end process;

end Behavioral;
