Commit 01d728ed authored by Matthieu Cattin's avatar Matthieu Cattin

Add wbgen files for test_ddr design.

parent b07d35bd
peripheral {
name = "Control and status registers";
description = "Wishbone slave to test CSR wishbone on SPEC board";
hdl_entity = "gpio_regs";
prefix = "gpio";
reg {
name = "Status";
prefix = "stat";
field {
name = "Status register";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Control_1";
prefix = "ctrl_1";
field {
name = "Control register 1";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Control_2";
prefix = "ctrl_2";
field {
name = "Control register 2";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Control_3";
prefix = "ctrl_3";
field {
name = "Control register 3";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "LED_control";
prefix = "led_ctrl";
field {
name = "Register for front panel LED control";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
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