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Simple PCIe FMC carrier SPEC
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Projects
Simple PCIe FMC carrier SPEC
Commits
0efc571f
Commit
0efc571f
authored
Sep 04, 2019
by
Federico Vaga
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Merge remote-tracking branch 'origin/proposed_master' into develop
parents
a750c98e
818b4c37
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16 changed files
with
256 additions
and
712 deletions
+256
-712
Manifest.py
hdl/rtl/Manifest.py
+1
-1
spec_base_regs.cheby
hdl/rtl/spec_base_regs.cheby
+1
-1
spec_base_regs.vhd
hdl/rtl/spec_base_regs.vhd
+225
-185
spec_base_wr.vhd
hdl/rtl/spec_base_wr.vhd
+6
-6
Manifest.py
hdl/syn/common/Manifest.py
+8
-7
spec_base_common.ucf
hdl/syn/common/spec_base_common.ucf
+2
-11
spec_base_ddr3.ucf
hdl/syn/common/spec_base_ddr3.ucf
+8
-8
spec_base_onewire.ucf
hdl/syn/common/spec_base_onewire.ucf
+0
-0
spec_base_spi.ucf
hdl/syn/common/spec_base_spi.ucf
+0
-0
spec_base_wr.ucf
hdl/syn/common/spec_base_wr.ucf
+1
-1
Manifest.py
hdl/syn/golden/Manifest.py
+1
-1
Manifest.py
hdl/syn/golden_wr/Manifest.py
+1
-1
spec_golden.ucf
hdl/top/golden/spec_golden.ucf
+0
-207
spec_golden.vhd
hdl/top/golden/spec_golden.vhd
+1
-1
spec_golden_wr.ucf
hdl/top/golden_wr/spec_golden_wr.ucf
+0
-281
spec_golden_wr.vhd
hdl/top/golden_wr/spec_golden_wr.vhd
+1
-1
No files found.
hdl/rtl/Manifest.py
View file @
0efc571f
files
=
[
"spec_
template_regs.vhd"
,
"spec_templat
e_wr.vhd"
]
files
=
[
"spec_
base_regs.vhd"
,
"spec_bas
e_wr.vhd"
]
hdl/rtl/spec_
templat
e_regs.cheby
→
hdl/rtl/spec_
bas
e_regs.cheby
View file @
0efc571f
memory-map:
name: spec_
templat
e_regs
name: spec_
bas
e_regs
bus: wb-32-be
size: 0x2000
children:
...
...
hdl/rtl/spec_
templat
e_regs.vhd
→
hdl/rtl/spec_
bas
e_regs.vhd
View file @
0efc571f
-- Do not edit; this file was generated by Cheby using these options:
-- --gen-hdl=spec_
template_regs.vhd -i spec_templat
e_regs.cheby
-- --gen-hdl=spec_
base_regs.vhd -i spec_bas
e_regs.cheby
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
wishbone_pkg
.
all
;
entity
spec_
templat
e_regs
is
entity
spec_
bas
e_regs
is
port
(
rst_n_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
...
...
@@ -26,6 +26,7 @@ entity spec_template_regs is
metadata_addr_o
:
out
std_logic_vector
(
5
downto
2
);
metadata_data_i
:
in
std_logic_vector
(
31
downto
0
);
metadata_data_o
:
out
std_logic_vector
(
31
downto
0
);
metadata_wr_o
:
out
std_logic
;
-- offset to the application metadata
csr_app_offset_i
:
in
std_logic_vector
(
31
downto
0
);
...
...
@@ -66,14 +67,15 @@ entity spec_template_regs is
buildinfo_addr_o
:
out
std_logic_vector
(
7
downto
2
);
buildinfo_data_i
:
in
std_logic_vector
(
31
downto
0
);
buildinfo_data_o
:
out
std_logic_vector
(
31
downto
0
);
buildinfo_wr_o
:
out
std_logic
;
-- white-rabbit core registers
wrc_regs_i
:
in
t_wishbone_master_in
;
wrc_regs_o
:
out
t_wishbone_master_out
);
end
spec_
templat
e_regs
;
end
spec_
bas
e_regs
;
architecture
syn
of
spec_
templat
e_regs
is
architecture
syn
of
spec_
bas
e_regs
is
signal
rd_int
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_ack_int
:
std_logic
;
...
...
@@ -131,21 +133,25 @@ begin
-- WB decode signals
wb_en
<=
wb_cyc_i
and
wb_stb_i
;
process
(
clk_i
,
rst_n_i
)
begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
wb_rip
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
else
wb_rip
<=
(
wb_rip
or
(
wb_en
and
not
wb_we_i
))
and
not
rd_ack_int
;
end
if
;
end
if
;
end
process
;
rd_int
<=
(
wb_en
and
not
wb_we_i
)
and
not
wb_rip
;
process
(
clk_i
,
rst_n_i
)
begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
wb_wip
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
else
wb_wip
<=
(
wb_wip
or
(
wb_en
and
wb_we_i
))
and
not
wr_ack_int
;
end
if
;
end
if
;
end
process
;
wr_int
<=
(
wb_en
and
wb_we_i
)
and
not
wb_wip
;
...
...
@@ -156,12 +162,14 @@ begin
wb_err_o
<=
'0'
;
-- Assign outputs
process
(
clk_i
,
rst_n_i
)
begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
metadata_rack
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
else
metadata_rack
<=
metadata_re
and
not
metadata_rack
;
end
if
;
end
if
;
end
process
;
metadata_data_o
<=
wb_dat_i
;
metadata_addr_o
<=
wb_adr_i
(
5
downto
2
);
...
...
@@ -170,12 +178,14 @@ begin
-- Assignments for submap therm_id
therm_id_tr
<=
therm_id_wt
or
therm_id_rt
;
process
(
clk_i
,
rst_n_i
)
begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
therm_id_rt
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
else
therm_id_rt
<=
(
therm_id_rt
or
therm_id_re
)
and
not
therm_id_rack
;
end
if
;
end
if
;
end
process
;
therm_id_o
.
cyc
<=
therm_id_tr
;
therm_id_o
.
stb
<=
therm_id_tr
;
...
...
@@ -188,12 +198,14 @@ begin
-- Assignments for submap fmc_i2c
fmc_i2c_tr
<=
fmc_i2c_wt
or
fmc_i2c_rt
;
process
(
clk_i
,
rst_n_i
)
begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
fmc_i2c_rt
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
else
fmc_i2c_rt
<=
(
fmc_i2c_rt
or
fmc_i2c_re
)
and
not
fmc_i2c_rack
;
end
if
;
end
if
;
end
process
;
fmc_i2c_o
.
cyc
<=
fmc_i2c_tr
;
fmc_i2c_o
.
stb
<=
fmc_i2c_tr
;
...
...
@@ -206,12 +218,14 @@ begin
-- Assignments for submap flash_spi
flash_spi_tr
<=
flash_spi_wt
or
flash_spi_rt
;
process
(
clk_i
,
rst_n_i
)
begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
flash_spi_rt
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
else
flash_spi_rt
<=
(
flash_spi_rt
or
flash_spi_re
)
and
not
flash_spi_rack
;
end
if
;
end
if
;
end
process
;
flash_spi_o
.
cyc
<=
flash_spi_tr
;
flash_spi_o
.
stb
<=
flash_spi_tr
;
...
...
@@ -224,12 +238,14 @@ begin
-- Assignments for submap dma
dma_tr
<=
dma_wt
or
dma_rt
;
process
(
clk_i
,
rst_n_i
)
begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
dma_rt
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
else
dma_rt
<=
(
dma_rt
or
dma_re
)
and
not
dma_rack
;
end
if
;
end
if
;
end
process
;
dma_o
.
cyc
<=
dma_tr
;
dma_o
.
stb
<=
dma_tr
;
...
...
@@ -242,12 +258,14 @@ begin
-- Assignments for submap vic
vic_tr
<=
vic_wt
or
vic_rt
;
process
(
clk_i
,
rst_n_i
)
begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
vic_rt
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
else
vic_rt
<=
(
vic_rt
or
vic_re
)
and
not
vic_rack
;
end
if
;
end
if
;
end
process
;
vic_o
.
cyc
<=
vic_tr
;
vic_o
.
stb
<=
vic_tr
;
...
...
@@ -257,24 +275,28 @@ begin
vic_o
.
sel
<=
(
others
=>
'1'
);
vic_o
.
we
<=
vic_wt
;
vic_o
.
dat
<=
wb_dat_i
;
process
(
clk_i
,
rst_n_i
)
begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
buildinfo_rack
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
else
buildinfo_rack
<=
buildinfo_re
and
not
buildinfo_rack
;
end
if
;
end
if
;
end
process
;
buildinfo_data_o
<=
wb_dat_i
;
buildinfo_addr_o
<=
wb_adr_i
(
7
downto
2
);
-- Assignments for submap wrc_regs
wrc_regs_tr
<=
wrc_regs_wt
or
wrc_regs_rt
;
process
(
clk_i
,
rst_n_i
)
begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
wrc_regs_rt
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
else
wrc_regs_rt
<=
(
wrc_regs_rt
or
wrc_regs_re
)
and
not
wrc_regs_rack
;
end
if
;
end
if
;
end
process
;
wrc_regs_o
.
cyc
<=
wrc_regs_tr
;
wrc_regs_o
.
stb
<=
wrc_regs_tr
;
...
...
@@ -286,9 +308,11 @@ begin
wrc_regs_o
.
dat
<=
wb_dat_i
;
-- Process for write requests.
process
(
clk_i
,
rst_n_i
)
begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
wr_ack_int
<=
'0'
;
metadata_wr_o
<=
'0'
;
csr_resets_global_reg
<=
'0'
;
csr_resets_appl_reg
<=
'0'
;
therm_id_wt
<=
'0'
;
...
...
@@ -296,14 +320,17 @@ begin
flash_spi_wt
<=
'0'
;
dma_wt
<=
'0'
;
vic_wt
<=
'0'
;
buildinfo_wr_o
<=
'0'
;
wrc_regs_wt
<=
'0'
;
elsif
rising_edge
(
clk_i
)
then
else
wr_ack_int
<=
'0'
;
metadata_wr_o
<=
'0'
;
therm_id_wt
<=
'0'
;
fmc_i2c_wt
<=
'0'
;
flash_spi_wt
<=
'0'
;
dma_wt
<=
'0'
;
vic_wt
<=
'0'
;
buildinfo_wr_o
<=
'0'
;
wrc_regs_wt
<=
'0'
;
case
wb_adr_i
(
12
downto
12
)
is
when
"0"
=>
...
...
@@ -312,6 +339,8 @@ begin
case
wb_adr_i
(
7
downto
6
)
is
when
"00"
=>
-- Submap metadata
metadata_wr_o
<=
wr_int
;
wr_ack_int
<=
wr_int
;
when
"01"
=>
case
wb_adr_i
(
5
downto
4
)
is
when
"00"
=>
...
...
@@ -374,6 +403,8 @@ begin
wr_ack_int
<=
vic_wack
;
when
"0010"
=>
-- Submap buildinfo
buildinfo_wr_o
<=
wr_int
;
wr_ack_int
<=
wr_int
;
when
others
=>
wr_ack_int
<=
wr_int
;
end
case
;
...
...
@@ -385,14 +416,15 @@ begin
wr_ack_int
<=
wr_int
;
end
case
;
end
if
;
end
if
;
end
process
;
-- Process for registers read.
process
(
clk_i
,
rst_n_i
)
begin
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_i
=
'0'
then
rd_ack1_int
<=
'0'
;
reg_rdat_int
<=
(
others
=>
'X'
);
elsif
rising_edge
(
clk_i
)
then
else
reg_rdat_int
<=
(
others
=>
'0'
);
case
wb_adr_i
(
12
downto
12
)
is
when
"0"
=>
...
...
@@ -422,6 +454,7 @@ begin
reg_rdat_int
<=
csr_gn4124_status_i
;
rd_ack1_int
<=
rd_int
;
when
others
=>
reg_rdat_int
<=
(
others
=>
'X'
);
rd_ack1_int
<=
rd_int
;
end
case
;
when
"01"
=>
...
...
@@ -435,10 +468,12 @@ begin
reg_rdat_int
(
3
downto
0
)
<=
csr_pcb_rev_rev_i
;
rd_ack1_int
<=
rd_int
;
when
others
=>
reg_rdat_int
<=
(
others
=>
'X'
);
rd_ack1_int
<=
rd_int
;
end
case
;
when
"11"
=>
when
others
=>
reg_rdat_int
<=
(
others
=>
'X'
);
rd_ack1_int
<=
rd_int
;
end
case
;
when
"10"
=>
...
...
@@ -446,22 +481,27 @@ begin
when
"0"
=>
when
"1"
=>
when
others
=>
reg_rdat_int
<=
(
others
=>
'X'
);
rd_ack1_int
<=
rd_int
;
end
case
;
when
"11"
=>
when
others
=>
reg_rdat_int
<=
(
others
=>
'X'
);
rd_ack1_int
<=
rd_int
;
end
case
;
when
"0001"
=>
when
"0010"
=>
when
others
=>
reg_rdat_int
<=
(
others
=>
'X'
);
rd_ack1_int
<=
rd_int
;
end
case
;
when
"1"
=>
when
others
=>
reg_rdat_int
<=
(
others
=>
'X'
);
rd_ack1_int
<=
rd_int
;
end
case
;
end
if
;
end
if
;
end
process
;
-- Process for read requests.
...
...
hdl/rtl/spec_
templat
e_wr.vhd
→
hdl/rtl/spec_
bas
e_wr.vhd
View file @
0efc571f
...
...
@@ -4,9 +4,9 @@
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_
templat
e_wr
-- unit name: spec_
bas
e_wr
--
-- description: SPEC carrier
template, with WR
.
-- description: SPEC carrier
base
.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
...
...
@@ -40,7 +40,7 @@ use work.streamers_pkg.all;
library
unisim
;
use
unisim
.
vcomponents
.
all
;
entity
spec_
templat
e_wr
is
entity
spec_
bas
e_wr
is
generic
(
-- If true, instantiate a VIC/ONEWIRE/SPI/WR/DDRAM+DMA.
g_WITH_VIC
:
boolean
:
=
True
;
...
...
@@ -291,9 +291,9 @@ entity spec_template_wr is
app_wb_o
:
out
t_wishbone_master_out
;
app_wb_i
:
in
t_wishbone_master_in
);
end
entity
spec_
templat
e_wr
;
end
entity
spec_
bas
e_wr
;
architecture
top
of
spec_
templat
e_wr
is
architecture
top
of
spec_
bas
e_wr
is
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant
c_WRPC_PLL_CONFIG
:
t_auxpll_cfg_array
:
=
(
0
=>
(
enabled
=>
TRUE
,
bufg_en
=>
TRUE
,
divide
=>
3
),
...
...
@@ -507,7 +507,7 @@ begin -- architecture top
master_o
(
1
)
=>
app_wb_o
);
inst_devs
:
entity
work
.
spec_
templat
e_regs
inst_devs
:
entity
work
.
spec_
bas
e_regs
port
map
(
rst_n_i
=>
rst_62m5_sys_n
,
clk_i
=>
clk_62m5_sys
,
...
...
hdl/syn/common/Manifest.py
View file @
0efc571f
files
=
[
"spec_
templat
e_common.ucf"
]
files
=
[
"spec_
bas
e_common.ucf"
]
ucf_dict
=
{
'wr'
:
"spec_template_wr.ucf"
,
'onewire'
:
"spec_template_onewire.ucf"
,
'spi'
:
"spec_template_spi.ucf"
,
'ddr3'
:
"spec_template_ddr3.ucf"
}
ucf_dict
=
{
'wr'
:
"spec_base_wr.ucf"
,
'onewire'
:
"spec_base_onewire.ucf"
,
'spi'
:
"spec_base_spi.ucf"
,
'ddr3'
:
"spec_base_ddr3.ucf"
,
'dma'
:
"spec_base_dma.ucf"
}
for
p
in
spec_
templat
e_ucf
:
for
p
in
spec_
bas
e_ucf
:
f
=
ucf_dict
.
get
(
p
,
None
)
assert
f
is
not
None
,
"unknown name {} in 'spec_
templat
e_ucf'"
.
format
(
p
)
assert
f
is
not
None
,
"unknown name {} in 'spec_
bas
e_ucf'"
.
format
(
p
)
files
.
append
(
f
)
hdl/syn/common/spec_
templat
e_common.ucf
→
hdl/syn/common/spec_
bas
e_common.ucf
View file @
0efc571f
...
...
@@ -152,8 +152,8 @@ NET "*/gc_reset_async_in" TIG;
# Declaration of domains
NET "inst_spec_
templat
e/clk_62m5_sys" TNM_NET = sys_clk;
NET "inst_spec_
templat
e/clk_125m_ref" TNM_NET = ref_clk;
NET "inst_spec_
bas
e/clk_62m5_sys" TNM_NET = sys_clk;
NET "inst_spec_
bas
e/clk_125m_ref" TNM_NET = ref_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_clk;
...
...
@@ -179,12 +179,3 @@ TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "sys_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_word_* (3x multicycle)
NET "*/gc_sync_word_data[*]" TNM = FFS "sync_word";
TIMESPEC TS_sys_sync_word = FROM sync_word TO sys_clk 48ns DATAPATHONLY;
TIMESPEC TS_ref_sync_word = FROM sync_word TO ref_clk 24ns DATAPATHONLY;
# no gc_sync_word used in GN4124
#TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY;
hdl/syn/common/spec_
templat
e_ddr3.ucf
→
hdl/syn/common/spec_
bas
e_ddr3.ucf
View file @
0efc571f
...
...
@@ -81,23 +81,23 @@ NET "ddr_udqs_n_b" IN_TERM = NONE;
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "inst_spec_
templat
e/*cmp_ddr_ctrl_bank?/*/c?_pll_lock" TIG;
NET "inst_spec_
templat
e/*cmp_ddr_ctrl_bank?/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "inst_spec_
templat
e/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "inst_
templat
e/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
NET "inst_spec_
bas
e/*cmp_ddr_ctrl_bank?/*/c?_pll_lock" TIG;
NET "inst_spec_
bas
e/*cmp_ddr_ctrl_bank?/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "inst_spec_
bas
e/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "inst_
bas
e/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
# Ignore async reset to DDR controller
NET "inst_spec_
templat
e/ddr_rst" TPTHRU = ddr_rst;
NET "inst_spec_
bas
e/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "inst_spec_
templat
e/clk_ddr_333m" TNM_NET = ddr_clk;
NET "inst_spec_
bas
e/clk_ddr_333m" TNM_NET = ddr_clk;
NET "inst_spec_
templat
e/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_spec_
templat
e/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
NET "inst_spec_
bas
e/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_spec_
bas
e/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
# DDR does not use any sync modules
...
...
hdl/syn/common/spec_
templat
e_onewire.ucf
→
hdl/syn/common/spec_
bas
e_onewire.ucf
View file @
0efc571f
File moved
hdl/syn/common/spec_
templat
e_spi.ucf
→
hdl/syn/common/spec_
bas
e_spi.ucf
View file @
0efc571f
File moved
hdl/syn/common/spec_
templat
e_wr.ucf
→
hdl/syn/common/spec_
bas
e_wr.ucf
View file @
0efc571f
...
...
@@ -75,7 +75,7 @@ TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "inst_spec_
templat
e/gen_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int[1]" TNM_NET = wrc_gtp_clk;
NET "inst_spec_
bas
e/gen_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int[1]" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
#-------------------------------------------------------------
...
...
hdl/syn/golden/Manifest.py
View file @
0efc571f
...
...
@@ -13,7 +13,7 @@ syn_project = "spec_golden.xise"
syn_tool
=
"ise"
syn_top
=
"spec_golden"
spec_
templat
e_ucf
=
[
'onewire'
,
'spi'
]
spec_
bas
e_ucf
=
[
'onewire'
,
'spi'
]
board
=
"spec"
ctrls
=
[
"bank3_64b_32b"
]
...
...
hdl/syn/golden_wr/Manifest.py
View file @
0efc571f
...
...
@@ -13,7 +13,7 @@ syn_project = "spec_golden_wr.xise"
syn_tool
=
"ise"
syn_top
=
"spec_golden_wr"
spec_
templat
e_ucf
=
[
'wr'
,
'onewire'
,
'spi'
]
spec_
bas
e_ucf
=
[
'wr'
,
'onewire'
,
'spi'
]
board
=
"spec"
ctrls
=
[
"bank3_64b_32b"
]
...
...
hdl/top/golden/spec_golden.ucf
deleted
100644 → 0
View file @
a750c98e
#bank 0
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#NET "SFP_MOD_DEF1_b" LOC = C17;
#NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF0_b" LOC = G15;
#NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF2_b" LOC = G16;
#NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_RATE_SELECT_b" LOC = H14;
#NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_FAULT_i" LOC = A17;
#NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_DISABLE_o" LOC = F17;
#NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
#NET "SFP_LOS_i" LOC = D18;
#NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
#NET "BUTTON1_I" LOC = C22;
#NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
#NET "BUTTON2_I" LOC = D21;
#NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "SPI_NCS_O" LOC = AA3;
NET "SPI_NCS_O" IOSTANDARD = "LVCMOS25";
NET "SPI_SCLK_O" LOC = Y20;
NET "SPI_SCLK_O" IOSTANDARD = "LVCMOS25";
NET "SPI_MOSI_O" LOC = AB20;
NET "SPI_MOSI_O" IOSTANDARD = "LVCMOS25";
NET "SPI_MISO_I" LOC = AA20;
NET "SPI_MISO_I" IOSTANDARD = "LVCMOS25";
NET "GN_RST_N" LOC = N20;
NET "GN_RST_N" IOSTANDARD = "LVCMOS18";
NET "GN_L2P_CLK_N" LOC = K22;
NET "GN_L2P_CLK_N" IOSTANDARD = "DIFF_SSTL18_I";
NET "GN_L2P_CLK_P" LOC = K21;
NET "GN_L2P_CLK_P" IOSTANDARD = "DIFF_SSTL18_I";
NET "GN_L2P_DFRAME" LOC = U22;
NET "GN_L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_EDB" LOC = U20;
NET "GN_L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_RDY" LOC = U19;
NET "GN_L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_VALID" LOC = T18;
NET "GN_L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "GN_L_WR_RDY[0]" LOC = R20;
NET "GN_L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "GN_L_WR_RDY[1]" LOC = T22;
NET "GN_L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_CLK_N" LOC = M19;
NET "GN_P2L_CLK_N" IOSTANDARD = "DIFF_SSTL18_I";
NET "GN_P2L_CLK_P" LOC = M20;
NET "GN_P2L_CLK_P" IOSTANDARD = "DIFF_SSTL18_I";
NET "GN_P2L_DFRAME" LOC = J22;
NET "GN_P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_RDY" LOC = J16;
NET "GN_P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_VALID" LOC = L19;
NET "GN_P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "GN_P_RD_D_RDY[0]" LOC = N16;
NET "GN_P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "GN_P_RD_D_RDY[1]" LOC = P19;
NET "GN_P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "GN_P_WR_RDY[0]" LOC = L15;
NET "GN_P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "GN_P_WR_RDY[1]" LOC = K16;
NET "GN_P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "GN_P_WR_REQ[0]" LOC = M22;
NET "GN_P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "GN_P_WR_REQ[1]" LOC = M21;
NET "GN_P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "GN_RX_ERROR" LOC = J17;
NET "GN_RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "GN_TX_ERROR" LOC = M17;
NET "GN_TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "GN_VC_RDY[0]" LOC = B21;
NET "GN_VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "GN_VC_RDY[1]" LOC = B22;
NET "GN_VC_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[0]" LOC = P16;
NET "GN_L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[1]" LOC = P21;
NET "GN_L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[2]" LOC = P18;
NET "GN_L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[3]" LOC = T20;
NET "GN_L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[4]" LOC = V21;
NET "GN_L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[5]" LOC = V19;
NET "GN_L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[6]" LOC = W22;
NET "GN_L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[7]" LOC = Y22;
NET "GN_L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[8]" LOC = P22;
NET "GN_L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[9]" LOC = R22;
NET "GN_L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[10]" LOC = T21;
NET "GN_L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[11]" LOC = T19;
NET "GN_L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[12]" LOC = V22;
NET "GN_L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[13]" LOC = V20;
NET "GN_L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[14]" LOC = W20;
NET "GN_L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "GN_L2P_DATA[15]" LOC = Y21;
NET "GN_L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[0]" LOC = K20;
NET "GN_P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[1]" LOC = H22;
NET "GN_P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[2]" LOC = H21;
NET "GN_P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[3]" LOC = L17;
NET "GN_P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[4]" LOC = K17;
NET "GN_P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[5]" LOC = G22;
NET "GN_P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[6]" LOC = G20;
NET "GN_P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[7]" LOC = K18;
NET "GN_P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[8]" LOC = K19;
NET "GN_P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[9]" LOC = H20;
NET "GN_P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[10]" LOC = J19;
NET "GN_P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[11]" LOC = E22;
NET "GN_P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[12]" LOC = E20;
NET "GN_P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[13]" LOC = F22;
NET "GN_P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[14]" LOC = F21;
NET "GN_P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "GN_P2L_DATA[15]" LOC = H19;
NET "GN_P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
# GPIO 8 and 9 of the Genum
NET "GN_GPIO[0]" LOC = U16;
NET "GN_GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "GN_GPIO[1]" LOC = AB19;
NET "GN_GPIO[1]" IOSTANDARD = "LVCMOS25";
#NET "LED_RED" LOC = D5;
#NET "LED_RED" IOSTANDARD = "LVCMOS25";
#NET "LED_GREEN" LOC = E5;
#NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
# Onewire interface -> thermometer
NET "onewire_b" LOC = D4;
NET "onewire_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot management
#----------------------------------------
NET "fmc0_prsnt_m2c_n_i" LOC = AB14;
NET "fmc0_scl_b" LOC = F7;
NET "fmc0_sda_b" LOC = F8;
NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
#---------------------------------------------------------------------------------------------
# False Path
#---------------------------------------------------------------------------------------------
# GN4124
NET "gn_rst_n" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "inst_template/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = inst_template/cmp_gn4124_core/cmp_clk_in/P_clk;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
NET "GN_P2L_CLK_p" TNM_NET = "p2l_clkp_grp";
NET "GN_P2L_CLK_n" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "inst_template/cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
hdl/top/golden/spec_golden.vhd
View file @
0efc571f
...
...
@@ -97,7 +97,7 @@ architecture rtl of spec_golden is
signal
gn_wb_out
:
t_wishbone_master_out
;
signal
gn_wb_in
:
t_wishbone_master_in
;
begin
inst_spec_
template
:
entity
work
.
spec_templat
e_wr
inst_spec_
base
:
entity
work
.
spec_bas
e_wr
generic
map
(
g_WITH_VIC
=>
True
,
g_WITH_ONEWIRE
=>
True
,
...
...
hdl/top/golden_wr/spec_golden_wr.ucf
deleted
100644 → 0
View file @
a750c98e
This diff is collapsed.
Click to expand it.
hdl/top/golden_wr/spec_golden_wr.vhd
View file @
0efc571f
...
...
@@ -160,7 +160,7 @@ architecture top of spec_golden_wr is
signal
gn_wb_out
:
t_wishbone_master_out
;
signal
gn_wb_in
:
t_wishbone_master_in
;
begin
inst_spec_
template
:
entity
work
.
spec_templat
e_wr
inst_spec_
base
:
entity
work
.
spec_bas
e_wr
generic
map
(
g_WITH_VIC
=>
True
,
g_WITH_ONEWIRE
=>
False
,
...
...
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