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Simple PCIe FMC carrier SPEC
Commit 19dd7856 authored by Matthieu Cattin's avatar Matthieu Cattin
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Update with new Gennum and DDR cores interfaces.

parent 10a0730a
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hdl/test_ddr/rtl/Manifest.py
View file @ 19dd7856
files = ["spec_ddr_test.vhd",
"gpio_regs.vhd"]
modules = {"svn" : ["http://svn.ohwr.org/gn4124-core/branches/xilinx_fifo/gn4124core/rtl",
"http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl",
"http://svn.ohwr.org/gn4124-core/branches/xilinx_fifo/spec/ip_cores"]}
modules = {"svn" : ["http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl",
"http://svn.ohwr.org/gn4124-core/trunk/hdl/common/rtl",
"http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl"],
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git"}
fetchto = "../ip_cores"
hdl/test_ddr/rtl/spec_ddr_test.vhd
View file @ 19dd7856
......@@ -118,26 +118,13 @@ architecture rtl of spec_ddr_test is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component gn4124_core
generic(
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26 -- DMA wishbone address bus width
);
port
(
---------------------------------------------------------
-- Control and status
--
-- Asynchronous reset from GN4124
rst_n_a_i : in std_logic;
-- P2L clock PLL locked
p2l_pll_locked : out std_logic;
-- Debug ouputs
debug_o : out std_logic_vector(7 downto 0);
rst_n_a_i : in std_logic; -- Asynchronous reset from GN4124
status_o : out std_logic_vector(31 downto 0); -- Core status output
---------------------------------------------------------
-- P2L Direction
......@@ -178,36 +165,88 @@ architecture rtl of spec_ddr_test is
irq_p_o : out std_logic; -- Interrupt request pulse to GN4124 GPIO
---------------------------------------------------------
-- Target interface (CSR wishbone master)
wb_clk_i : in std_logic;
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_CSR_WB_SLAVES_NB+1)-1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_cyc_o : out std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
wb_dat_i : in std_logic_vector((32*g_CSR_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_CSR_WB_SLAVES_NB-1 downto 0);
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i : in std_logic;
dma_reg_adr_i : in std_logic_vector(31 downto 0);
dma_reg_dat_i : in std_logic_vector(31 downto 0);
dma_reg_sel_i : in std_logic_vector(3 downto 0);
dma_reg_stb_i : in std_logic;
dma_reg_we_i : in std_logic;
dma_reg_cyc_i : in std_logic;
dma_reg_dat_o : out std_logic_vector(31 downto 0);
dma_reg_ack_o : out std_logic;
dma_reg_stall_o : out std_logic;
---------------------------------------------------------
-- CSR wishbone interface (master pipelined)
csr_clk_i : in std_logic;
csr_adr_o : out std_logic_vector(31 downto 0);
csr_dat_o : out std_logic_vector(31 downto 0);
csr_sel_o : out std_logic_vector(3 downto 0);
csr_stb_o : out std_logic;
csr_we_o : out std_logic;
csr_cyc_o : out std_logic;
csr_dat_i : in std_logic_vector(31 downto 0);
csr_ack_i : in std_logic;
csr_stall_i : in std_logic;
---------------------------------------------------------
-- DMA interface (Pipelined wishbone master)
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(31 downto 0); -- Data out
dma_sel_o : out std_logic_vector(3 downto 0); -- Byte select
dma_dat_o : out std_logic_vector(31 downto 0);
dma_sel_o : out std_logic_vector(3 downto 0);
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_cyc_o : out std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_dat_i : in std_logic_vector((32*g_DMA_WB_SLAVES_NB)-1 downto 0); -- Data in
dma_ack_i : in std_logic; --_vector(g_DMA_WB_SLAVES_NB-1 downto 0);
dma_stall_i : in std_logic--_vector(g_DMA_WB_SLAVES_NB-1 downto 0) -- for pipelined Wishbone
dma_cyc_o : out std_logic;
dma_dat_i : in std_logic_vector(31 downto 0);
dma_ack_i : in std_logic;
dma_stall_i : in std_logic
);
end component; -- gn4124_core
component wb_addr_decoder
generic
(
g_WINDOW_SIZE : integer := 18; -- Number of bits to address periph on the board (32-bit word address)
g_WB_SLAVES_NB : integer := 2
);
port
(
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i : in std_logic;
rst_n_i : in std_logic;
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i : in std_logic_vector(31 downto 0); -- Address
wbm_dat_i : in std_logic_vector(31 downto 0); -- Data out
wbm_sel_i : in std_logic_vector(3 downto 0); -- Byte select
wbm_stb_i : in std_logic; -- Strobe
wbm_we_i : in std_logic; -- Write
wbm_cyc_i : in std_logic; -- Cycle
wbm_dat_o : out std_logic_vector(31 downto 0); -- Data in
wbm_ack_o : out std_logic; -- Acknowledge
wbm_stall_o : out std_logic; -- Stall
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o : out std_logic_vector(31 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Acknowledge
wb_stall_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Stall
);
end component wb_addr_decoder;
component ddr3_ctrl
generic(
g_MEMCLK_PERIOD : integer := 3200; -- in ps
g_RST_ACT_LOW : integer := 1; -- 1=active low
g_SIMULATION : string := "FALSE";
g_CALIB_SOFT_IP : string := "TRUE";
g_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN"; -- BANK_ROW_COLUMN or ROW_BANK_COLUMN
......@@ -225,7 +264,7 @@ architecture rtl of spec_ddr_test is
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
calib_done : out std_logic;
status_o : out std_logic_vector(31 downto 0);
ddr3_dq_b : inout std_logic_vector(g_NUM_DQ_PINS-1 downto 0);
ddr3_a_o : out std_logic_vector(g_MEM_ADDR_WIDTH-1 downto 0);
ddr3_ba_o : out std_logic_vector(g_MEM_BANKADDR_WIDTH-1 downto 0);
......@@ -251,7 +290,7 @@ architecture rtl of spec_ddr_test is
wb0_cyc_i : in std_logic;
wb0_stb_i : in std_logic;
wb0_we_i : in std_logic;
wb0_addr_i : in std_logic_vector(g_P0_BYTE_ADDR_WIDTH - 3 downto 0);
wb0_addr_i : in std_logic_vector(31 downto 0);
wb0_data_i : in std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_data_o : out std_logic_vector(g_P0_DATA_PORT_SIZE - 1 downto 0);
wb0_ack_o : out std_logic;
......@@ -262,7 +301,7 @@ architecture rtl of spec_ddr_test is
wb1_cyc_i : in std_logic;
wb1_stb_i : in std_logic;
wb1_we_i : in std_logic;
wb1_addr_i : in std_logic_vector(g_P1_BYTE_ADDR_WIDTH - 3 downto 0);
wb1_addr_i : in std_logic_vector(31 downto 0);
wb1_data_i : in std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
wb1_data_o : out std_logic_vector(g_P1_DATA_PORT_SIZE - 1 downto 0);
wb1_ack_o : out std_logic;
......@@ -294,10 +333,8 @@ architecture rtl of spec_ddr_test is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_BAR0_APERTURE : integer := 20;
constant c_CSR_WB_SLAVES_NB : integer := 3;
constant c_DMA_WB_SLAVES_NB : integer := 1;
constant c_DMA_WB_ADDR_WIDTH : integer := 26;
constant c_BAR0_APERTURE : integer := 18; -- nb of bits for 32-bit word address
constant c_CSR_WB_SLAVES_NB : integer := 2;
------------------------------------------------------------------------------
-- Signals declaration
......@@ -325,30 +362,38 @@ architecture rtl of spec_ddr_test is
-- Reset
signal rst : std_logic;
-- CSR wishbone bus
signal wb_adr : std_logic_vector(c_BAR0_APERTURE-log2_ceil(c_CSR_WB_SLAVES_NB+1)-1 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal spi_wb_adr : std_logic_vector(4 downto 0);
signal ddr_wb_adr : std_logic_vector(26 downto 0);
-- CSR wishbone bus (master)
signal wbm_adr : std_logic_vector(31 downto 0);
signal wbm_dat_i : std_logic_vector(31 downto 0);
signal wbm_dat_o : std_logic_vector(31 downto 0);
signal wbm_sel : std_logic_vector(3 downto 0);
signal wbm_cyc : std_logic;
signal wbm_stb : std_logic;
signal wbm_we : std_logic;
signal wbm_ack : std_logic;
signal wbm_stall : std_logic;
-- CSR wishbone bus (slaves)
signal wb_adr : std_logic_vector(31 downto 0);
signal wb_dat_i : std_logic_vector((32*c_CSR_WB_SLAVES_NB)-1 downto 0);
signal wb_dat_o : std_logic_vector(31 downto 0);
signal wb_sel : std_logic_vector(3 downto 0);
signal wb_cyc : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
signal wb_stall : std_logic_vector(c_CSR_WB_SLAVES_NB-1 downto 0);
-- DMA wishbone bus
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_dat_i : std_logic_vector((32*c_DMA_WB_SLAVES_NB)-1 downto 0);
signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal dma_cyc : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal dma_stb : std_logic;
signal dma_we : std_logic;
signal dma_ack : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal dma_stall : std_logic; --_vector(c_DMA_WB_SLAVES_NB-1 downto 0);
signal ram_we : std_logic_vector(0 downto 0);
signal ddr_dma_adr : std_logic_vector(27 downto 0);
signal dma_adr : std_logic_vector(31 downto 0);
signal dma_dat_i : std_logic_vector(31 downto 0);
signal dma_dat_o : std_logic_vector(31 downto 0);
signal dma_sel : std_logic_vector(3 downto 0);
signal dma_cyc : std_logic;
signal dma_stb : std_logic;
signal dma_we : std_logic;
signal dma_ack : std_logic;
signal dma_stall : std_logic;
-- Interrupts stuff
signal irq_sources : std_logic_vector(1 downto 0);
......@@ -363,8 +408,12 @@ architecture rtl of spec_ddr_test is
signal gpio_led_ctrl : std_logic_vector(31 downto 0);
-- DDR3
signal ddr3_status : std_logic_vector(31 downto 0);
signal ddr3_calib_done : std_logic;
-- Gennum core
signal gn4124_status : std_logic_vector(31 downto 0);
-- LED
signal led_cnt1 : unsigned(22 downto 0);
signal led_cnt2 : unsigned(24 downto 0);
......@@ -456,21 +505,13 @@ begin
-- GN4124 interface
------------------------------------------------------------------------------
cmp_gn4124_core : gn4124_core
generic map (
g_BAR0_APERTURE => c_BAR0_APERTURE,
g_CSR_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB,
g_DMA_WB_SLAVES_NB => c_DMA_WB_SLAVES_NB,
g_DMA_WB_ADDR_WIDTH => c_DMA_WB_ADDR_WIDTH)
port map(
port map
(
---------------------------------------------------------
-- Control and status
--
-- Asynchronous reset from GN4124
rst_n_a_i => L_RST_N,
-- P2L clock PLL locked
p2l_pll_locked => p2l_pll_locked,
-- Debug outputs
debug_o => open,
rst_n_a_i => L_RST_N,
status_o => gn4124_status,
---------------------------------------------------------
-- P2L Direction
......@@ -513,19 +554,33 @@ begin
irq_p_o => GPIO(0),
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i => sys_clk_50,
wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
wb_sel_o => wb_sel,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
wb_ack_i => wb_ack,
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => sys_clk_50,
dma_reg_adr_i => wb_adr,
dma_reg_dat_i => wb_dat_o,
dma_reg_sel_i => wb_sel,
dma_reg_stb_i => wb_stb,
dma_reg_we_i => wb_we,
dma_reg_cyc_i => wb_cyc(0),
dma_reg_dat_o => wb_dat_i(31 downto 0),
dma_reg_ack_o => wb_ack(0),
dma_reg_stall_o => wb_stall(0),
---------------------------------------------------------
-- DMA wishbone interface (pipelined)
-- CSR wishbone interface (master pipelined)
csr_clk_i => sys_clk_50,
csr_adr_o => wbm_adr,
csr_dat_o => wbm_dat_o,
csr_sel_o => wbm_sel,
csr_stb_o => wbm_stb,
csr_we_o => wbm_we,
csr_cyc_o => wbm_cyc,
csr_dat_i => wbm_dat_i,
csr_ack_i => wbm_ack,
csr_stall_i => wbm_stall,
---------------------------------------------------------
-- DMA wishbone interface (master pipelined)
dma_clk_i => sys_clk_50,
dma_adr_o => dma_adr,
dma_dat_o => dma_dat_o,
......@@ -535,13 +590,54 @@ begin
dma_cyc_o => dma_cyc,
dma_dat_i => dma_dat_i,
dma_ack_i => dma_ack,
dma_stall_i => dma_stall);
dma_stall_i => dma_stall
);
p2l_pll_locked <= gn4124_status(0);
------------------------------------------------------------------------------
-- CSR wishbone address decoder
------------------------------------------------------------------------------
cmp_csr_wb_addr_decoder : wb_addr_decoder
generic map (
g_WINDOW_SIZE => c_BAR0_APERTURE,
g_WB_SLAVES_NB => c_CSR_WB_SLAVES_NB
)
port map (
---------------------------------------------------------
-- GN4124 core clock and reset
clk_i => sys_clk_50,
rst_n_i => L_RST_N,
---------------------------------------------------------
-- wishbone master interface
wbm_adr_i => wbm_adr,
wbm_dat_i => wbm_dat_o,
wbm_sel_i => wbm_sel,
wbm_stb_i => wbm_stb,
wbm_we_i => wbm_we,
wbm_cyc_i => wbm_cyc,
wbm_dat_o => wbm_dat_i,
wbm_ack_o => wbm_ack,
wbm_stall_o => wbm_stall,
---------------------------------------------------------
-- wishbone slaves interface
wb_adr_o => wb_adr,
wb_dat_o => wb_dat_o,
wb_sel_o => wb_sel,
wb_stb_o => wb_stb,
wb_we_o => wb_we,
wb_cyc_o => wb_cyc,
wb_dat_i => wb_dat_i,
wb_ack_i => wb_ack,
wb_stall_i => wb_stall
);
------------------------------------------------------------------------------
-- CSR wishbone bus slaves
-- 0 -> Not connected
-- 0 -> DMA control and status registers (inside gn4124 core)
-- 1 -> gpio registers
-- 2 -> DDR3 controller port0
------------------------------------------------------------------------------
cmp_gpio_regs : gpio_regs
port map(
......@@ -561,6 +657,8 @@ begin
gpio_ctrl_3_o => gpio_ctrl_3,
gpio_led_ctrl_o => gpio_led_ctrl);
wb_stall(1) <= '0';
gpio_stat <= X"DEAD000"
& '0'
& ddr3_calib_done
......@@ -619,12 +717,15 @@ begin
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
g_P0_MASK_SIZE => 4,
g_P0_DATA_PORT_SIZE => 32,
g_P0_BYTE_ADDR_WIDTH => 30)
g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32,
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => ddr_clk,
rst_n_i => L_RST_N,
calib_done => ddr3_calib_done,
status_o => ddr3_status,
ddr3_dq_b => DDR3_DQ,
ddr3_a_o => DDR3_A,
......@@ -651,23 +752,25 @@ begin
wb0_cyc_i => '0', --wb_cyc(2), --'0',
wb0_stb_i => '0', --wb_stb, --'0',
wb0_we_i => '0', --wb_we, --'0',
wb0_addr_i => X"0000000",
wb0_addr_i => X"00000000",
wb0_data_i => X"00000000", --wb_dat_o, --X"00000000",
wb0_data_o => open, --wb_dat_i(95 downto 64), --open,
wb0_ack_o => open, --wb_ack(2), --open,
wb0_stall_o => open,
wb1_clk_i => sys_clk_50,
wb1_sel_i => "1111",
wb1_sel_i => dma_sel,
wb1_cyc_i => dma_cyc,
wb1_stb_i => dma_stb,
wb1_we_i => dma_we,
wb1_addr_i => dma_adr(27 downto 0),
wb1_addr_i => dma_adr,
wb1_data_i => dma_dat_o,
wb1_data_o => dma_dat_i,
wb1_ack_o => dma_ack,
wb1_stall_o => dma_stall);
ddr3_calib_done <= ddr3_status(0);
------------------------------------------------------------------------------
-- Assign unused outputs
------------------------------------------------------------------------------
......
hdl/test_ddr/spec_ddr_test.ucf
View file @ 19dd7856
......@@ -568,11 +568,11 @@ NET "DDR3_UDQS_N" IN_TERM = NONE;
# GN4124
NET "L_CLKp" TNM_NET = "l_clkp_grp";
TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 6.25 ns HIGH 50%;
TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 6.25 ns HIGH 50%;
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 6.25 ns HIGH 50%;
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50%;
# System clock
......@@ -599,3 +599,4 @@ NET "cmp_gn4124_core/rst_*" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/cmp_ddr_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/cmp_ddr_ctrl/c3_pll_lock" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/cmp_ddr_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/cmp_ddr_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
hdl/test_ddr/syn/spec_ddr_test.xise
View file @ 19dd7856
......@@ -9,17 +9,627 @@
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="blk_mem_gen_v4_1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
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<library xil_pn:name="blk_mem_gen_v4_1"/>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
<file xil_pn:name="../spec_ddr_test.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -30,9 +640,10 @@
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -71,6 +682,7 @@
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -113,7 +725,6 @@
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -155,12 +766,14 @@
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
......@@ -182,6 +795,7 @@
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -223,11 +837,11 @@
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="TB_SPEC_synthesis.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="TB_SPEC_translate.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
......@@ -241,6 +855,7 @@
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
......@@ -289,12 +904,14 @@
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.TB_SPEC" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="default"/>
......@@ -305,6 +922,7 @@
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -357,118 +975,27 @@
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-07-12T10:43:38" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A4459BBB5563DB49840D3D7DB31402AB" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries/>
<files>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/spec/ip_cores/fifo_64x512.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/spec/ip_cores/fifo_32x512.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../spec_ddr_test.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr_ctrl_bank3/user_design/rtl/ddr_ctrl_bank3.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_wb_single.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/spec_ddr_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/spec/ip_cores/fifo_64x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/spec/ip_cores/fifo_32x512.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../rtl/gpio_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/branches/xilinx_fifo/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
</files>
<bindings/>
<version xil_pn:ise_version="12.2" xil_pn:schema_version="2"/>
<libraries>
<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</libraries>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
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