Commit 2320ebe1 authored by Matthieu Cattin's avatar Matthieu Cattin

Add manifests, rename top module and synthesis dir.

parent 4efbf377
files = ["spec_ddr_test_top.vhd",
"gpio_regs.vhd"]
modules = {"svn" : ["http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl",
"http://svn.ohwr.org/ddr3-sp6-core/trunk/hdl/spec/rtl"]}
......@@ -31,7 +31,7 @@ library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top is
entity spec_ddr_test is
generic(
g_SIMULATION : string := "FALSE";
g_CALIB_SOFT_IP : string := "TRUE");
......@@ -106,10 +106,10 @@ entity spec_top is
DDR3_ZIO : inout std_logic;
DDR3_RZQ : inout std_logic
);
end spec_top;
end spec_ddr_test;
architecture rtl of spec_top is
architecture rtl of spec_ddr_test is
------------------------------------------------------------------------------
-- Components declaration
......
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_ddr_test"
syn_project = "spec_ddr_test.xise"
files = ["../spec_ddr_test.ucf"]
modules = { "local" : "../rtl" }
......@@ -26,19 +26,19 @@
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/gn4124_core_pkg_s6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/l2p_ser_s6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/p2l_des_s6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
......@@ -70,19 +70,19 @@
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../../GN4124_core/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
......
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