spec template: support aux clocks, rename clock signals

Also change g_simulation type.

spec template: support aux clocks, rename clock signals
Also change g_simulation type.
41d53adb · Tristan Gingold · 778af94f · 41d53adb
Commit 41d53adb authored Sep 04, 2019 by Tristan Gingold
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Showing with 81 additions and 63 deletions

spec_template_wr.vhd hdl/rtl/spec_template_wr.vhd +81 -63

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--- a/hdl/rtl/spec_template_wr.vhd
+++ b/hdl/rtl/spec_template_wr.vhd