hdl: fixed DDR reset polarity

4c3ac537 · Evangelia Gousiou · aa4d4ff2 · 4c3ac537
Commit 4c3ac537 authored Jun 16, 2020 by Evangelia Gousiou
Hide whitespace changes
Inline Side-by-side

Showing with 5 additions and 1 deletion

spec_base_wr.vhd hdl/rtl/spec_base_wr.vhd +5 -1

No files found.
--- a/hdl/rtl/spec_base_wr.vhd
+++ b/hdl/rtl/spec_base_wr.vhd
@@ -392,6 +392,7 @@ architecture top of spec_base_wr is
  signal rst_125m_ref_n : std_logic;
  signal clk_125m_ref   : std_logic;
  signal clk_10m_ext    : std_logic;
+  signal ddr_rst_n      : std_logic;

  -- I2C EEPROM
  signal eeprom_sda_in  : std_logic;
@@ -1035,6 +1036,9 @@ begin  -- architecture top
  end generate;

  --  DDR3 controller
+
+  ddr_rst_n <= not ddr_rst;
+
  gen_with_ddr: if g_WITH_DDR generate
    function get_ddr3_bank_port_select return string is
    begin
@@ -1062,7 +1066,7 @@ begin  -- architecture top
        g_P1_BYTE_ADDR_WIDTH => 30)
      port map (
        clk_i   => clk_333m_ddr,
-        rst_n_i => ddr_rst,
+        rst_n_i => ddr_rst_n,

        status_o => ddr_status,