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Simple PCIe FMC carrier SPEC
Commit 62fcd2fe authored by Greg Daniluk's avatar Greg Daniluk
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adding golden FPGA binary

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hdl/golden/Manifest.py 0 → 100644
View file @ 62fcd2fe
fetchto = "ip_cores"
modules = {"local" : [ "platform" ],
"git" : "git://ohwr.org/hdl-core-lib/wr-cores.git"
}
hdl/golden/platform/Manifest.py 0 → 100644
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modules = {"local" : "xilinx"}
hdl/golden/platform/xilinx/Manifest.py 0 → 100644
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files = [ "wr_xilinx_pkg.vhd" ]
modules = {"local" : ["wr_gtp_phy", "chipscope"]}
\ No newline at end of file
hdl/golden/platform/xilinx/chipscope/Manifest.py 0 → 100644
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files =["chipscope_icon.ngc", "chipscope_ila.ngc" ]
hdl/golden/platform/xilinx/chipscope/chipscope_icon.ngc 0 → 100644
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hdl/golden/platform/xilinx/chipscope/chipscope_ila.ngc 0 → 100644
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hdl/golden/platform/xilinx/wr_gtp_phy/Manifest.py 0 → 100644
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files = ["gtp_bitslide.vhd",
"gtp_phase_align.vhd",
"gtp_phase_align_virtex6.vhd",
"gtx_reset.vhd",
"whiterabbitgtx_wrapper_gtx.vhd",
# "whiterabbitgtp_wrapper.vhd",
"whiterabbitgtp_wrapper_tile.vhd",
"wr_gtp_phy_spartan6.vhd",
"wr_gtx_phy_virtex6.vhd"];
hdl/golden/platform/xilinx/wr_gtp_phy/gtp_bitslide.vhd 0 → 100644
View file @ 62fcd2fe
-------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - bitslide state machine
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_bitslide.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Module implements a manual bitslide alignment state machine and
-- provides the obtained bitslide value to the MAC.
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN / Tomasz Wlostowski
--
-- <license>
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Ported EASE design to VHDL
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP
-- 2011-09-12 0.6 twlostow Virtex6 port
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtp_bitslide is
generic (
-- set to non-zero value to enable some simulation speedups (reduce delays)
g_simulation : integer;
g_target : string := "spartan6");
port (
gtp_rst_i : in std_logic;
-- GTP
gtp_rx_clk_i : in std_logic;
-- '1' indicates that the GTP has detected a comma in the incoming serial stream
gtp_rx_comma_det_i : in std_logic;
gtp_rx_byte_is_aligned_i : in std_logic;
-- GTP ready flag (PLL locked and RX signal present)
serdes_ready_i : in std_logic;
-- GTP manual bitslip control line
gtp_rx_slide_o : out std_logic;
-- GTP CDR reset, asserted when the link is lost to set the bitslide to a known
-- value
gtp_rx_cdr_rst_o : out std_logic;
-- Current bitslide, in UIs
bitslide_o : out std_logic_vector(4 downto 0);
-- '1' when the bitsliding has been completed and the link is up
synced_o : out std_logic
);
end gtp_bitslide;
architecture behavioral of gtp_bitslide is
function f_eval_sync_detect_threshold
return integer is
begin
if(g_simulation /= 0) then
return 256;
elsif(g_target = "spartan6") then
return 8192;
else
return 16384;
end if;
end f_eval_sync_detect_threshold;
function f_eval_pause_tics return integer is
begin
if(g_target = "spartan6") then
return 31;
else
return 63;
end if;
end f_eval_pause_tics;
constant c_pause_tics : integer := f_eval_pause_tics;
constant c_sync_detect_threshold : integer := f_eval_sync_detect_threshold;
type t_bitslide_fsm_state is (S_SYNC_LOST, S_STABILIZE, S_SLIDE, S_PAUSE, S_GOT_SYNC, S_RESET_CDR);
signal cur_slide : unsigned(4 downto 0);
signal state : t_bitslide_fsm_state;
signal counter : unsigned(15 downto 0);
signal commas_missed : unsigned(1 downto 0);
begin -- behavioral
p_do_slide : process(gtp_rx_clk_i, gtp_rst_i)
begin
if gtp_rst_i = '1' then
state <= S_SYNC_LOST;
gtp_rx_slide_o <= '0';
counter <= (others => '0');
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
elsif rising_edge(gtp_rx_clk_i) then
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
case state is
-- State: synchronization lost. Waits until a comma pattern is detected
when S_SYNC_LOST =>
cur_slide <= (others => '0');
counter <= (others => '0');
gtp_rx_slide_o <= '0';
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
commas_missed <= (others => '0');
if(gtp_rx_comma_det_i = '1') then
state <= S_STABILIZE;
end if;
-- State: stabilize:
when S_STABILIZE =>
if(gtp_rx_comma_det_i = '1') then
counter <= counter + 1;
commas_missed <= (others => '0');
else
commas_missed <= commas_missed + 1;
if(commas_missed(1) = '1') then
state <= S_SYNC_LOST;
end if;
end if;
if(counter = to_unsigned(c_sync_detect_threshold, counter'length)) then
counter <= (others => '0');
state <= S_PAUSE;
end if;
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
when S_SLIDE =>
cur_slide <= cur_slide + 1;
gtp_rx_slide_o <= '1';
counter <= (others => '0');
state <= S_PAUSE;
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
when S_PAUSE =>
counter <= counter + 1;
gtp_rx_slide_o <= '0';
if(counter = to_unsigned(c_pause_tics, counter'length)) then
if(gtp_rx_byte_is_aligned_i = '0') then
state <= S_SLIDE;
else
state <= S_GOT_SYNC;
end if;
end if;
when S_GOT_SYNC =>
gtp_rx_slide_o <= '0';
bitslide_o <= std_logic_vector(cur_slide);
synced_o <= '1';
if(gtp_rx_byte_is_aligned_i = '0' or serdes_ready_i = '0') then
gtp_rx_cdr_rst_o <= '1';
state <= S_SYNC_LOST;
end if;
when others => null;
end case;
end if;
end process;
end behavioral;
hdl/golden/platform/xilinx/wr_gtp_phy/gtp_phase_align.vhd 0 → 100644
View file @ 62fcd2fe
------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - TX phase alignment
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_phase_align.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: TX phase alignment state machine, as recommended by Xilinx.
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN / Tomasz Wlostowski
--
-- <license>
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Ported EASE design to VHDL
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtp_phase_align is
generic
(g_simulation : integer);
port (
gtp_rst_i : in std_logic;
gtp_tx_clk_i : in std_logic;
gtp_tx_en_pma_phase_align_o : out std_logic;
gtp_tx_pma_set_phase_o : out std_logic;
align_en_i : in std_logic;
align_done_o : out std_logic
);
end gtp_phase_align;
architecture behavioral of gtp_phase_align is
constant c_wait_en_phase_align : integer := 32;
constant c_wait_set_phase_align : integer := 512;
constant c_phase_align_duration : integer := 8192;
type t_align_state is (S_ALIGN_IDLE, S_ALIGN_PAUSE, S_ALIGN_WAIT, S_ALIGN_SET_PHASE, S_ALIGN_DONE);
signal counter : unsigned(13 downto 0);
signal state : t_align_state;
begin -- behavioral
p_align : process(gtp_tx_clk_i, gtp_rst_i)
begin
if rising_edge(gtp_tx_clk_i) then
if gtp_rst_i = '1' then
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
counter <= (others => '0');
align_done_o <= '0';
state <= S_ALIGN_IDLE;
else
if(align_en_i = '0') then
state <= S_ALIGN_IDLE;
else
case (state) is
when S_ALIGN_IDLE =>
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
counter <= (others => '0');
align_done_o <= '0';
if(align_en_i = '1') then
state <= S_ALIGN_PAUSE;
end if;
when S_ALIGN_PAUSE =>
counter <= counter + 1;
if(counter = to_unsigned(c_wait_en_phase_align, counter'length)) then
state <= S_ALIGN_WAIT;
end if;
when S_ALIGN_WAIT =>
gtp_tx_en_pma_phase_align_o <= '1';
counter <= counter + 1;
if(counter = to_unsigned(c_wait_en_phase_align + c_wait_set_phase_align, counter'length)) then
state <= S_ALIGN_SET_PHASE;
end if;
when S_ALIGN_SET_PHASE =>
counter <= counter +1;
gtp_tx_pma_set_phase_o <= '1';
if(counter = to_unsigned(c_wait_en_phase_align + c_wait_set_phase_align + c_phase_align_duration, counter'length)) then
state <= S_ALIGN_DONE;
end if;
when S_ALIGN_DONE =>
gtp_tx_pma_set_phase_o <= '0';
counter <= (others => '0');
align_done_o <= '1';
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
hdl/golden/platform/xilinx/wr_gtp_phy/gtp_phase_align_virtex6.vhd 0 → 100644
View file @ 62fcd2fe
------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - TX phase alignment
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_phase_align.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: TX phase alignment state machine, as recommended by Xilinx.
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN / Tomasz Wlostowski
--
-- <license>
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Ported EASE design to VHDL
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP
-- 2011-09-12 0.6 twlostow Virtex6 port
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtp_phase_align_virtex6 is
generic
(g_simulation : integer);
port (
gtp_rst_i : in std_logic;
gtp_tx_clk_i : in std_logic;
gtp_tx_en_pma_phase_align_o : out std_logic;
gtp_tx_pma_set_phase_o : out std_logic;
gtp_tx_dly_align_disable_o : out std_logic;
gtp_tx_dly_align_reset_o : out std_logic;
align_en_i : in std_logic;
align_done_o : out std_logic
);
end gtp_phase_align_virtex6;
architecture behavioral of gtp_phase_align_virtex6 is
constant c_dly_align_reset_time : integer := 16;
constant c_wait_set_phase_align : integer := 32;
constant c_phase_align_duration : integer := 8192;
type t_align_state is (S_ALIGN_IDLE, S_DLY_ALIGN_RESET, S_ALIGN_WAIT, S_ALIGN_SET_PHASE, S_ALIGN_DONE);
signal counter : unsigned(13 downto 0);
signal state : t_align_state;
begin -- behavioral
p_align : process(gtp_tx_clk_i, gtp_rst_i)
begin
if rising_edge(gtp_tx_clk_i) then
if gtp_rst_i = '1' then
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
gtp_tx_dly_align_reset_o <= '0';
gtp_tx_dly_align_disable_o <= '1';
counter <= (others => '0');
align_done_o <= '0';
state <= S_ALIGN_IDLE;
else
if(align_en_i = '0') then
state <= S_ALIGN_IDLE;
else
case (state) is
when S_ALIGN_IDLE =>
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
gtp_tx_dly_align_reset_o <= '0';
gtp_tx_dly_align_disable_o <= '1';
counter <= (others => '0');
align_done_o <= '0';
if(align_en_i = '1') then
state <= S_DLY_ALIGN_RESET;
end if;
when S_DLY_ALIGN_RESET =>
counter <= counter + 1;
gtp_tx_dly_align_reset_o <= '1';
gtp_tx_dly_align_disable_o <= '1';
if(counter = to_unsigned(c_dly_align_reset_time, counter'length)) then
state <= S_ALIGN_WAIT;
end if;
when S_ALIGN_WAIT =>
gtp_tx_dly_align_reset_o <= '0';
gtp_tx_dly_align_disable_o <= '1';
gtp_tx_en_pma_phase_align_o <= '1';
counter <= counter + 1;
if(counter = to_unsigned(c_dly_align_reset_time + c_wait_set_phase_align, counter'length)) then
state <= S_ALIGN_SET_PHASE;
end if;
when S_ALIGN_SET_PHASE =>
counter <= counter +1;
gtp_tx_pma_set_phase_o <= '1';
if(counter = to_unsigned(c_dly_align_reset_time + c_wait_set_phase_align + c_phase_align_duration, counter'length)) then
state <= S_ALIGN_DONE;
end if;
when S_ALIGN_DONE =>
gtp_tx_pma_set_phase_o <= '0';
gtp_tx_dly_align_disable_o <= '0';
counter <= (others => '0');
align_done_o <= '1';
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
hdl/golden/platform/xilinx/wr_gtp_phy/gtx_reset.vhd 0 → 100644
View file @ 62fcd2fe
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtx_reset is
port (
clk_tx_i : in std_logic;
rst_i : in std_logic;
txpll_lockdet_i : in std_logic;
gtx_test_o : out std_logic_vector(12 downto 0)
);
end gtx_reset;
architecture behavioral of gtx_reset is
type t_state is (IDLE, PAUSE, FIRST_RST, PAUSE2, SECOND_RST, DONE);
signal state : t_state;
signal counter : unsigned(15 downto 0);
begin -- behavioral
process(clk_tx_i)
begin
if rising_edge(clk_tx_i) then
if rst_i = '1' then
state <= IDLE;
counter <= (others => '0');
else
if(txpll_lockdet_i = '0') then
state <= IDLE;
else
case state is
when IDLE =>
counter <= (others => '0');
gtx_test_o <= "1000000000000";
if(txpll_lockdet_i = '1') then
state <= PAUSE;
end if;
when PAUSE =>
counter <= counter + 1;
gtx_test_o <= "1000000000000";
if(counter = 1024) then
state <= FIRST_RST;
end if;
when FIRST_RST =>
counter <= counter + 1;
gtx_test_o <= "1000000000010";
if(counter = 1024 + 256) then
state <= PAUSE2;
end if;
when PAUSE2=>
counter <= counter + 1;
gtx_test_o <= "1000000000000";
if(counter = 1024 + 2*256) then
state <= SECOND_RST;
end if;
when SECOND_RST =>
counter <= counter + 1;
gtx_test_o <= "1000000000010";
if(counter = 1024 + 3*256) then
state <= DONE;
end if;
when DONE =>
gtx_test_o <= "1000000000000";
end case;
end if;
end if;
end if;
end process;
end behavioral;
hdl/golden/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spartan6.vhd 0 → 100644
View file @ 62fcd2fe
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hdl/golden/platform/xilinx/wr_gtp_phy/wr_gtp_phy_spec.vhd 0 → 100644
View file @ 62fcd2fe
library ieee;
use ieee.std_logic_1164.all;
entity wr_gtp_phy_spec_wrapper is
generic (
g_simulation : integer := 0);
port(
sfp_ref_clk_i : in std_logic;
sfp_ref_clk_o : out std_logic;
sfp_tx_data_i : in std_logic_vector(7 downto 0);
sfp_tx_k_i : in std_logic;
sfp_tx_disparity_o : out std_logic;
sfp_tx_enc_err_o : out std_logic;
sfp_rx_rbclk_o : out std_logic;
sfp_rx_data_o : out std_logic_vector(7 downto 0);
sfp_rx_k_o : out std_logic;
sfp_rx_enc_err_o : out std_logic;
sfp_rx_bitslide_o : out std_logic_vector(3 downto 0);
sfp_rst_i : in std_logic;
sfp_loopen_i : in std_logic;
sfp_txn_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_rxn_i : in std_logic;
sfp_rxp_i : in std_logic;
sata0_ref_clk_i : in std_logic;
sata0_ref_clk_o : out std_logic;
sata0_tx_data_i : in std_logic_vector(7 downto 0);
sata0_tx_k_i : in std_logic;
sata0_tx_disparity_o : out std_logic;
sata0_tx_enc_err_o : out std_logic;
sata0_rx_rbclk_o : out std_logic;
sata0_rx_data_o : out std_logic_vector(7 downto 0);
sata0_rx_k_o : out std_logic;
sata0_rx_enc_err_o : out std_logic;
sata0_rx_bitslide_o : out std_logic_vector(3 downto 0);
sata0_rst_i : in std_logic;
sata0_loopen_i : in std_logic;
sata0_txn_o : out std_logic;
sata0_txp_o : out std_logic;
sata0_rxn_i : in std_logic;
sata0_rxp_i : in std_logic;
sata1_ref_clk_i : in std_logic;
sata1_ref_clk_o : out std_logic;
sata1_tx_data_i : in std_logic_vector(7 downto 0);
sata1_tx_k_i : in std_logic;
sata1_tx_disparity_o : out std_logic;
sata1_tx_enc_err_o : out std_logic;
sata1_rx_rbclk_o : out std_logic;
sata1_rx_data_o : out std_logic_vector(7 downto 0);
sata1_rx_k_o : out std_logic;
sata1_rx_enc_err_o : out std_logic;
sata1_rx_bitslide_o : out std_logic_vector(3 downto 0);
sata1_rst_i : in std_logic;
sata1_loopen_i : in std_logic;
sata1_txn_o : out std_logic;
sata1_txp_o : out std_logic;
sata1_rxn_i : in std_logic;
sata1_rxp_i : in std_logic;
fmc_ref_clk_i : in std_logic;
fmc_ref_clk_o : out std_logic;
fmc_tx_data_i : in std_logic_vector(7 downto 0);
fmc_tx_k_i : in std_logic;
fmc_tx_disparity_o : out std_logic;
fmc_tx_enc_err_o : out std_logic;
fmc_rx_rbclk_o : out std_logic;
fmc_rx_data_o : out std_logic_vector(7 downto 0);
fmc_rx_k_o : out std_logic;
fmc_rx_enc_err_o : out std_logic;
fmc_rx_bitslide_o : out std_logic_vector(3 downto 0);
fmc_rst_i : in std_logic;
fmc_loopen_i : in std_logic;
fmc_txn_o : out std_logic;
fmc_txp_o : out std_logic;
fmc_rxn_i : in std_logic;
fmc_rxp_i : in std_logic
);
end wr_gtp_phy_spec_wrapper;
architecture rtl of wr_gtp_phy_spec_wrapper is
component wr_gtp_phy_spartan6
generic (
g_simulation : integer);
port (
ch0_ref_clk_i : in std_logic;
ch0_ref_clk_o : out std_logic;
ch0_tx_data_i : in std_logic_vector(7 downto 0);
ch0_tx_k_i : in std_logic;
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic;
ch0_loopen_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_ref_clk_o : out std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
begin -- rtl
U_GTP1 : wr_gtp_phy_spartan6
generic map (
g_simulation => g_simulation)
port map (
ch0_ref_clk_i => fmc_ref_clk_i,
ch0_ref_clk_o => fmc_ref_clk_o,
ch0_tx_data_i => fmc_tx_data_i,
ch0_tx_k_i => fmc_tx_k_i,
ch0_tx_disparity_o => fmc_tx_disparity_o,
ch0_tx_enc_err_o => fmc_tx_enc_err_o,
ch0_rx_rbclk_o => fmc_rx_rbclk_o,
ch0_rx_data_o => fmc_rx_data_o,
ch0_rx_k_o => fmc_rx_k_o,
ch0_rx_enc_err_o => fmc_rx_enc_err_o,
ch0_rx_bitslide_o => fmc_rx_bitslide_o,
ch0_rst_i => fmc_rst_i,
ch0_loopen_i => fmc_loopen_i,
ch1_ref_clk_i => sata0_ref_clk_i,
ch1_ref_clk_o => sata0_ref_clk_o,
ch1_tx_data_i => sata0_tx_data_i,
ch1_tx_k_i => sata0_tx_k_i,
ch1_tx_disparity_o => sata0_tx_disparity_o,
ch1_tx_enc_err_o => sata0_tx_enc_err_o,
ch1_rx_data_o => sata0_rx_data_o,
ch1_rx_rbclk_o => sata0_rx_rbclk_o,
ch1_rx_k_o => sata0_rx_k_o,
ch1_rx_enc_err_o => sata0_rx_enc_err_o,
ch1_rx_bitslide_o => sata0_rx_bitslide_o,
ch1_rst_i => sata0_rst_i,
ch1_loopen_i => sata0_loopen_i,
pad_txn0_o => fmc_txn_o,
pad_txp0_o => fmc_txp_o,
pad_rxn0_i => fmc_rxn_i,
pad_rxp0_i => fmc_rxp_i,
pad_txn1_o => sata0_txn_o,
pad_txp1_o => sata0_txp_o,
pad_rxn1_i => sata0_rxn_i,
pad_rxp1_i => sata0_rxp_i);
U_GTP2 : wr_gtp_phy_spartan6
generic map (
g_simulation => g_simulation)
port map (
ch0_ref_clk_i => sata1_ref_clk_i,
ch0_ref_clk_o => sata1_ref_clk_o,
ch0_tx_data_i => sata1_tx_data_i,
ch0_tx_k_i => sata1_tx_k_i,
ch0_tx_disparity_o => sata1_tx_disparity_o,
ch0_tx_enc_err_o => sata1_tx_enc_err_o,
ch0_rx_rbclk_o => sata1_rx_rbclk_o,
ch0_rx_data_o => sata1_rx_data_o,
ch0_rx_k_o => sata1_rx_k_o,
ch0_rx_enc_err_o => sata1_rx_enc_err_o,
ch0_rx_bitslide_o => sata1_rx_bitslide_o,
ch0_rst_i => sata1_rst_i,
ch0_loopen_i => sata1_loopen_i,
ch1_ref_clk_i => sfp_ref_clk_i,
ch1_ref_clk_o => sfp_ref_clk_o,
ch1_tx_data_i => sfp_tx_data_i,
ch1_tx_k_i => sfp_tx_k_i,
ch1_tx_disparity_o => sfp_tx_disparity_o,
ch1_tx_enc_err_o => sfp_tx_enc_err_o,
ch1_rx_data_o => sfp_rx_data_o,
ch1_rx_rbclk_o => sfp_rx_rbclk_o,
ch1_rx_k_o => sfp_rx_k_o,
ch1_rx_enc_err_o => sfp_rx_enc_err_o,
ch1_rx_bitslide_o => sfp_rx_bitslide_o,
ch1_rst_i => sfp_rst_i,
ch1_loopen_i => sfp_loopen_i,
pad_txn0_o => sata1_txn_o,
pad_txp0_o => sata1_txp_o,
pad_rxn0_i => sata1_rxn_i,
pad_rxp0_i => sata1_rxp_i,
pad_txn1_o => sfp_txn_o,
pad_txp1_o => sfp_txp_o,
pad_rxn1_i => sfp_rxn_i,
pad_rxp1_i => sfp_rxp_i);
end rtl;
hdl/golden/platform/xilinx/wr_gtp_phy/wr_gtx_phy_virtex6.vhd 0 → 100644
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hdl/golden/platform/xilinx/wr_xilinx_pkg.vhd 0 → 100644
View file @ 62fcd2fe
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.genram_pkg.all;
use work.wishbone_pkg.all;
use work.sysc_wbgen2_pkg.all;
use work.wr_fabric_pkg.all;
package wr_xilinx_pkg is
component wr_gtp_phy_spartan6
generic (
g_simulation : integer);
port (
gtp_clk_i : in std_logic;
ch0_ref_clk_i : in std_logic;
ch0_tx_data_i : in std_logic_vector(7 downto 0);
ch0_tx_k_i : in std_logic;
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);
ch0_rx_k_o : out std_logic;
ch0_rx_enc_err_o : out std_logic;
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic;
ch0_loopen_i : in std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
ch1_tx_k_i : in std_logic := '0';
ch1_tx_disparity_o : out std_logic;
ch1_tx_enc_err_o : out std_logic;
ch1_rx_data_o : out std_logic_vector(7 downto 0);
ch1_rx_rbclk_o : out std_logic;
ch1_rx_k_o : out std_logic;
ch1_rx_enc_err_o : out std_logic;
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
pad_rxn0_i : in std_logic := '0';
pad_rxp0_i : in std_logic := '0';
pad_txn1_o : out std_logic;
pad_txp1_o : out std_logic;
pad_rxn1_i : in std_logic := '0';
pad_rxp1_i : in std_logic := '0');
end component;
end wr_xilinx_pkg;
hdl/golden/syn/Makefile 0 → 100644
View file @ 62fcd2fe
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := spec_init.xise
ISE_CRAP := *.b spec_init_summary.html *.tcl spec_init.bld spec_init.cmd_log *.drc spec_init.lso *.ncd spec_init.ngc spec_init.ngd spec_init.ngr spec_init.pad spec_init.par spec_init.pcf spec_init.prj spec_init.ptwx spec_init.stx spec_init.syr spec_init.twr spec_init.twx spec_init.gise spec_init.unroutes spec_init.ut spec_init.xpi spec_init.xst spec_init_bitgen.xwbt spec_init_envsettings.html spec_init_guide.ncd spec_init_map.map spec_init_map.mrp spec_init_map.ncd spec_init_map.ngm spec_init_map.xrpt spec_init_ngdbuild.xrpt spec_init_pad.csv spec_init_pad.txt spec_init_par.xrpt spec_init_summary.xml spec_init_usage.xml spec_init_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
hdl/golden/syn/Manifest.py 0 → 100644
View file @ 62fcd2fe
target = "xilinx"
action = "synthesis"
fetchto = "../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_top = "spec_init"
syn_project = "spec_init.xise"
modules = { "local" :
[ "../top",
"../platform/xilinx/chipscope" ]
}
hdl/golden/syn/spec_init.xise 0 → 100644
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hdl/golden/top/Manifest.py 0 → 100644
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files = ["spec_init.vhd", "spec_init.ucf"]
fetchto = "../ip_cores"
modules = {
"local" : ["../"],
"svn" : [ "http://svn.ohwr.org/gn4124-core/trunk/hdl/gn4124core/rtl" ]
}
hdl/golden/top/spec_init.ucf 0 → 100644
View file @ 62fcd2fe
#bank 0
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
NET "SFP_MOD_DEF1_b" LOC = C17;
NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF0_b" LOC = G15;
NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
NET "SFP_MOD_DEF2_b" LOC = G16;
NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
NET "SFP_RATE_SELECT_b" LOC = H14;
NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_FAULT_i" LOC = A17;
NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
NET "SFP_TX_DISABLE_o" LOC = F17;
NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
NET "SFP_LOS_i" LOC = D18;
NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
NET "FPGA_SCL_B" LOC = F7;
NET "FPGA_SCL_B" IOSTANDARD = "LVCMOS25";
NET "FPGA_SDA_B" LOC = F8;
NET "FPGA_SDA_B" IOSTANDARD = "LVCMOS25";
NET "BUTTON1_I" LOC = C22;
NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "GPIO[1]" LOC = U16;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
NET "GPIO[0]" LOC = AB19;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "LED_RED" LOC = D5;
NET "LED_RED" IOSTANDARD = "LVCMOS25";
NET "LED_GREEN" LOC = E5;
NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
#---------------------------------------------------------------------------------------------
# False Path
#---------------------------------------------------------------------------------------------
# GN4124
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
NET "cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = cmp_gn4124_core/cmp_clk_in/P_clk;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
hdl/golden/top/spec_init.vhd 0 → 100644
View file @ 62fcd2fe
This diff is collapsed.
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