Commit 641548d0 authored by Greg Daniluk's avatar Greg Daniluk

add SPI gpio to golden for accessing FLASH

parent 61bc524b
fetchto = "ip_cores"
modules = {"local" : [ "platform" ],
"git" : "git://ohwr.org/hdl-core-lib/wr-cores.git"
modules = {
"git" : "git://ohwr.org/hdl-core-lib/wr-cores.git::spi-flash",
"git" : "git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master"
}
......@@ -11,5 +11,7 @@ syn_project = "spec_init.xise"
modules = { "local" :
[ "../top",
"../platform/xilinx/chipscope" ]
"../ip_cores/general-cores",
"../ip_cores/gn4124-core",
"../ip_cores/wr-cores" ]
}
......@@ -31,6 +31,14 @@ NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "SPI_NCS_O" LOC = AA3;
NET "SPI_NCS_O" IOSTANDARD = "LVCMOS25";
NET "SPI_SCLK_O" LOC = Y20;
NET "SPI_SCLK_O" IOSTANDARD = "LVCMOS25";
NET "SPI_MOSI_O" LOC = AB20;
NET "SPI_MOSI_O" IOSTANDARD = "LVCMOS25";
NET "SPI_MISO_I" LOC = AA20;
NET "SPI_MISO_I" IOSTANDARD = "LVCMOS25";
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
......
......@@ -87,6 +87,11 @@ entity spec_init is
button1_i : in std_logic;
button2_i : in std_logic;
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
-------------------------------------------------------------------------
-- SFP pins
-------------------------------------------------------------------------
......@@ -388,6 +393,10 @@ begin
memsize_i => "0000",
btn1_i => button1_i,
btn2_i => button2_i,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
slave_i => periph_slv_in,
slave_o => periph_slv_out,
......
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