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Simple PCIe FMC carrier SPEC
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Simple PCIe FMC carrier SPEC
Commits
6fdc725f
Commit
6fdc725f
authored
Nov 15, 2013
by
Greg Daniluk
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add SPI gpio to golden for accessing FLASH
parent
f3132a44
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4 changed files
with
23 additions
and
3 deletions
+23
-3
Manifest.py
hdl/golden/Manifest.py
+3
-2
Manifest.py
hdl/golden/syn/Manifest.py
+3
-1
spec_init.ucf
hdl/golden/top/spec_init.ucf
+8
-0
spec_init.vhd
hdl/golden/top/spec_init.vhd
+9
-0
No files found.
hdl/golden/Manifest.py
View file @
6fdc725f
fetchto
=
"ip_cores"
modules
=
{
"local"
:
[
"platform"
],
"git"
:
"git://ohwr.org/hdl-core-lib/wr-cores.git"
modules
=
{
"git"
:
"git://ohwr.org/hdl-core-lib/wr-cores.git::spi-flash"
,
"git"
:
"git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master"
}
hdl/golden/syn/Manifest.py
View file @
6fdc725f
...
...
@@ -11,5 +11,7 @@ syn_project = "spec_init.xise"
modules
=
{
"local"
:
[
"../top"
,
"../platform/xilinx/chipscope"
]
"../ip_cores/general-cores"
,
"../ip_cores/gn4124-core"
,
"../ip_cores/wr-cores"
]
}
hdl/golden/top/spec_init.ucf
View file @
6fdc725f
...
...
@@ -31,6 +31,14 @@ NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
NET "BUTTON2_I" LOC = D21;
NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
NET "SPI_NCS_O" LOC = AA3;
NET "SPI_NCS_O" IOSTANDARD = "LVCMOS25";
NET "SPI_SCLK_O" LOC = Y20;
NET "SPI_SCLK_O" IOSTANDARD = "LVCMOS25";
NET "SPI_MOSI_O" LOC = AB20;
NET "SPI_MOSI_O" IOSTANDARD = "LVCMOS25";
NET "SPI_MISO_I" LOC = AA20;
NET "SPI_MISO_I" IOSTANDARD = "LVCMOS25";
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
...
...
hdl/golden/top/spec_init.vhd
View file @
6fdc725f
...
...
@@ -87,6 +87,11 @@ entity spec_init is
button1_i
:
in
std_logic
;
button2_i
:
in
std_logic
;
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
spi_miso_i
:
in
std_logic
;
-------------------------------------------------------------------------
-- SFP pins
-------------------------------------------------------------------------
...
...
@@ -388,6 +393,10 @@ begin
memsize_i
=>
"0000"
,
btn1_i
=>
button1_i
,
btn2_i
=>
button2_i
,
spi_sclk_o
=>
spi_sclk_o
,
spi_ncs_o
=>
spi_ncs_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
,
slave_i
=>
periph_slv_in
,
slave_o
=>
periph_slv_out
,
...
...
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