Commit 70af77d1 authored by Matthieu Cattin's avatar Matthieu Cattin

Altium project with EDA structure.

parent aef099f5
Files Generated : 0
Documents Printed : 0
Finished Output Generation At 1:35:13 PM On 10/18/2010
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_clocks|SchDesignator=U_clocks|FileName=clocks.SchDoc|SymbolType=Normal|RawFileName=clocks.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_fmc_connector|SchDesignator=U_fmc_connector|FileName=fmc_connector.SchDoc|SymbolType=Normal|RawFileName=fmc_connector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_fpga_gtp|SchDesignator=U_fpga_gtp|FileName=fpga_gtp.SchDoc|SymbolType=Normal|RawFileName=fpga_gtp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_fpga_io_bank_0|SchDesignator=U_fpga_io_bank_0|FileName=fpga_io_bank_0.SchDoc|SymbolType=Normal|RawFileName=fpga_io_bank_0.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_fpga_io_bank_1_PCIe|SchDesignator=U_fpga_io_bank_1_PCIe|FileName=fpga_io_bank_1_PCIe.SchDoc|SymbolType=Normal|RawFileName=fpga_io_bank_1_PCIe.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_fpga_io_bank_2_fmc|SchDesignator=U_fpga_io_bank_2_fmc|FileName=fpga_io_bank_2_fmc.SchDoc|SymbolType=Normal|RawFileName=fpga_io_bank_2_fmc.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_fpga_io_bank_3_ddr3|SchDesignator=U_fpga_io_bank_3_ddr3|FileName=fpga_io_bank_3_ddr3.SchDoc|SymbolType=Normal|RawFileName=fpga_io_bank_3_ddr3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_fpga_power|SchDesignator=U_fpga_power|FileName=fpga_power.SchDoc|SymbolType=Normal|RawFileName=fpga_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_jtga_chain|SchDesignator=U_jtga_chain|FileName=JTAG&CONFIG.SchDoc|SymbolType=Normal|RawFileName=JTAG&CONFIG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_PCIE_CON|SchDesignator=U_PCIE_CON|FileName=PCIE_CON.SchDoc|SymbolType=Normal|RawFileName=PCIE_CON.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_PCIe_LB_bridge|SchDesignator=U_PCIe_LB_bridge|FileName=PCIe_LB_bridge.SchDoc|SymbolType=Normal|RawFileName=PCIe_LB_bridge.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_pcie_power|SchDesignator=U_pcie_power|FileName=pcie_power.SchDoc|SymbolType=Normal|RawFileName=pcie_power.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_power_supply_linear|SchDesignator=U_power_supply_linear|FileName=power_supply_linear.SchDoc|SymbolType=Normal|RawFileName=power_supply_linear.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_power_supply_switching|SchDesignator=U_power_supply_switching|FileName=power_supply_switching.SchDoc|SymbolType=Normal|RawFileName=power_supply_switching.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_sfp|SchDesignator=U_sfp|FileName=sfp.SchDoc|SymbolType=Normal|RawFileName=sfp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=TopLevelDocument|FileName=FMC_PCIe_Carrier.SchDoc
---------------------------------------------------------------------------
NCDrill File Report For: EDA-02189-V1-0.pcbdoc 19/10/2010 16:34:00
---------------------------------------------------------------------------
Layer Pair : Top Layer to Bottom Layer
ASCII Plated RoundHoles File : EDA-02189-V1-0-Plated.TXT
ASCII Non-Plated RoundHoles File : EDA-02189-V1-0-NonPlated.TXT
EIA File : EDA-02189-V1-0.DRL
Tool Hole Size Hole Type Hole Count Plated Tool Travel
---------------------------------------------------------------------------
T1 7.9mil (0.20066mm) Round 1923 151.21 Inch (3840.62 mm)
T2 8mil (0.2032mm) Round 4 0.51 Inch (13.07 mm)
T3 11.8mil (0.29972mm) Round 9 3.30 Inch (83.71 mm)
T4 15.7mil (0.39878mm) Round 43 6.78 Inch (172.19 mm)
T5 33.5mil (0.8509mm) Round 1 0.00 Inch (0.00 mm)
T6 35.4mil (0.89916mm) Round 32 9.84 Inch (249.95 mm)
T7 39.4mil (1.00076mm) Round 4 0.30 Inch (7.62 mm)
T8 41.3mil (1.04902mm) Round 10 3.59 Inch (91.22 mm)
T9 51.2mil (1.30048mm) Round 10 9.89 Inch (251.33 mm)
T10 55.1mil (1.39954mm) Round 1 0.00 Inch (0.00 mm)
T11 66.9mil (1.69926mm) Round 5 1.83 Inch (46.50 mm)
T12 106.3mil (2.70002mm) Round 4 6.53 Inch (165.95 mm)
T13 126mil (3.2004mm) Round 2 3.63 Inch (92.14 mm)
T14 37.4mil (0.94996mm) Round 9 NPTH 2.27 Inch (57.74 mm)
T15 51.2mil (1.30048mm) Round 2 NPTH 2.14 Inch (54.47 mm)
T16 61mil (1.5494mm) Round 2 NPTH 0.38 Inch (9.60 mm)
---------------------------------------------------------------------------
Totals 2061 202.21 Inch (5136.10 mm)
Total Processing Time (hh:mm:ss) : 00:00:02
------------------------------------------------------------------------------------------
Gerber File Extension Report For: EDA-02189-V1-0.GBR 19/10/2010 16:34:03
------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
Layer Extension Layer Description
------------------------------------------------------------------------------------------
.GTS Top Solder
.GBS Bottom Solder
.GD1 Drill Drawing
------------------------------------------------------------------------------------------
Layer Pairs Export File for PCB: S:\nlopez\Altium\EDA-02189-V1-0_VANDERBIJ-Simple_PCIe_FMC_Carrier\PCB-Layout\EDA-02189-V1-0.pcbdoc
LayersSetName=Top_Bot_Plated_Thru_Holes|DrillFile=eda-02189-v1-0-plated.txt|LayerPairs=gtl,gbl
LayersSetName=Top_Bot_NonPlated_Thru_Holes|DrillFile=eda-02189-v1-0-nonplated.txt|LayerPairs=gtl,gbl
*************************************************************
FileName = EDA-02189-V1-0.GBR
AutoAperture = True
*************************************************************
Generating : Top Solder
File : EDA-02189-V1-0.GTS
Adding Layer : Top Solder
Adding Layer : Mechanical 1
Adding Layer : Corners
Adding Layer : Title Block
Adding Layer : Top Layer
Adding Layer : Multi-Layer
Used DCodes :
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
D64
D65
D66
D67
D68
D69
D70
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
D81
D82
D83
D84
*************************************************************
*************************************************************
Generating : Bottom Solder
File : EDA-02189-V1-0.GBS
Adding Layer : Bottom Solder
Adding Layer : Mechanical 1
Adding Layer : Corners
Adding Layer : Title Block
Adding Layer : Bottom Layer
Adding Layer : Multi-Layer
Used DCodes :
D10
D11
D12
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D32
D34
D43
D53
D67
D68
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92
D93
*************************************************************
*************************************************************
Generating : Drill Drawing
File : EDA-02189-V1-0.GD1
Adding Layer : Mechanical 1
Adding Layer : Corners
Adding Layer : Title Block
Adding Drill Pair : Top Layer-Bottom Layer
Adding Layer : Drill Drawing
Used DCodes :
D12
D15
D16
D17
D18
D94
D95
D96
D97
D98
D99
*************************************************************
D10 ROUNDED 125.000 125.000 0.000 LINE 0.000
D11 ROUNDED 225.000 225.000 0.000 LINE 0.000
D12 ROUNDED 7.000 7.000 0.000 LINE 0.000
D13 RECTANGULAR 1350.389 393.701 0.000 FLASH 0.000
D14 RECTANGULAR 314.960 135.827 0.000 FLASH 0.000
D15 ROUNDED 50.000 50.000 0.000 LINE 0.000
D16 ROUNDED 12.000 12.000 0.000 LINE 0.000
D17 ROUNDED 10.000 10.000 0.000 LINE 0.000
D18 ROUNDED 5.000 5.000 0.000 LINE 0.000
D19 RECTANGULAR 45.433 49.370 0.000 FLASH 180.000
D20 RECTANGULAR 45.433 49.370 0.000 FLASH 90.000
D21 RECTANGULAR 33.622 33.622 0.000 FLASH 90.000
D22 RECTANGULAR 34.409 34.409 0.000 FLASH 0.000
D23 RECTANGULAR 34.409 34.409 0.000 FLASH 270.000
D24 RECTANGULAR 47.402 49.370 0.000 FLASH 0.000
D25 RECTANGULAR 47.402 49.370 0.000 FLASH 270.000
D26 RECTANGULAR 78.740 78.740 0.000 FLASH 315.000
D27 RECTANGULAR 33.622 21.811 0.000 FLASH 0.000
D28 RECTANGULAR 92.677 61.181 0.000 FLASH 90.000
D29 RECTANGULAR 43.465 21.811 0.000 FLASH 90.000
D30 RECTANGULAR 78.898 71.024 0.000 FLASH 90.000
D31 RECTANGULAR 53.307 45.433 0.000 FLASH 180.000
D32 RECTANGULAR 80.866 55.276 0.000 FLASH 90.000
D33 RECTANGULAR 88.740 80.866 0.000 FLASH 90.000
D34 RECTANGULAR 33.622 33.622 0.000 FLASH 180.000
D35 ROUNDED 78.740 78.740 0.000 FLASH 0.000
D36 ROUNDED 27.716 27.716 0.000 FLASH 0.000
D37 ROUNDED 29.685 29.685 0.000 FLASH 0.000
D38 ROUNDED 25.748 25.748 0.000 FLASH 0.000
D39 RECTANGULAR 67.087 27.716 0.000 FLASH 180.000
D40 RECTANGULAR 33.622 71.024 0.000 FLASH 90.000
D41 RECTANGULAR 70.827 61.181 0.000 FLASH 180.000
D42 RECTANGULAR 94.646 76.929 0.000 FLASH 90.000
D43 RECTANGULAR 67.087 55.276 0.000 FLASH 270.000
D44 ROUNDED 45.433 21.811 0.000 FLASH 180.000
D45 ROUNDED 45.433 21.811 0.000 FLASH 270.000
D46 RECTANGULAR 149.764 149.764 0.000 FLASH 180.000
D47 RECTANGULAR 61.181 55.276 0.000 FLASH 90.000
D48 RECTANGULAR 137.953 137.953 0.000 FLASH 0.000
D49 ROUNDED 51.339 23.779 0.000 FLASH 90.000
D50 ROUNDED 51.339 23.779 0.000 FLASH 0.000
D51 RECTANGULAR 43.465 21.811 0.000 FLASH 0.000
D52 RECTANGULAR 108.425 78.898 0.000 FLASH 90.000
D53 RECTANGULAR 80.866 55.276 0.000 FLASH 180.000
D54 RECTANGULAR 124.173 222.598 0.000 FLASH 180.000
D55 RECTANGULAR 69.055 27.716 0.000 FLASH 270.000
D56 RECTANGULAR 33.622 90.709 0.000 FLASH 180.000
D57 RECTANGULAR 33.622 76.929 0.000 FLASH 90.000
D58 RECTANGULAR 69.055 27.716 0.000 FLASH 180.000
D59 RECTANGULAR 124.961 119.843 0.000 FLASH 180.000
D60 RECTANGULAR 177.126 160.000 0.000 FLASH 180.000
D61 ROUNDED 40.945 17.323 0.000 FLASH 180.000
D62 ROUNDED 40.945 17.323 0.000 FLASH 270.000
D63 RECTANGULAR 105.906 105.906 0.000 FLASH 270.000
D64 RECTANGULAR 47.402 65.118 0.000 FLASH 180.000
D65 RECTANGULAR 124.961 119.843 0.000 FLASH 270.000
D66 RECTANGULAR 88.740 29.685 0.000 FLASH 180.000
D67 RECTANGULAR 37.559 167.480 0.000 FLASH 0.000
D68 RECTANGULAR 37.559 135.984 0.000 FLASH 0.000
D69 RECTANGULAR 108.425 78.898 0.000 FLASH 0.000
D70 ROUNDED 35.197 35.197 0.000 FLASH 0.000
D71 ROUNDED 39.370 39.370 0.000 FLASH 0.000
D72 RECTANGULAR 88.740 88.740 0.000 FLASH 0.000
D73 ROUNDED 88.740 88.740 0.000 FLASH 0.000
D74 ROUNDED 69.055 69.055 0.000 FLASH 0.000
D75 RECTANGULAR 69.055 69.055 0.000 FLASH 180.000
D76 ROUNDED 72.992 72.992 0.000 FLASH 0.000
D77 ROUNDED 104.488 104.488 0.000 FLASH 0.000
D78 ROUNDED 92.677 92.677 0.000 FLASH 0.000
D79 ROUNDED 206.850 206.850 0.000 FLASH 0.000
D80 ROUNDED 238.346 238.346 0.000 FLASH 0.000
D81 ROUNDED 61.417 61.417 0.000 FLASH 0.000
D82 ROUNDED 76.929 76.929 0.000 FLASH 0.000
D83 ROUNDED 246.220 246.220 0.000 FLASH 0.000
D84 ROUNDED 62.992 62.992 0.000 FLASH 0.000
D85 RECTANGULAR 1350.394 393.706 0.000 FLASH 0.000
D86 RECTANGULAR 78.740 78.740 0.000 FLASH 225.000
D87 RECTANGULAR 47.402 65.118 0.000 FLASH 90.000
D88 RECTANGULAR 49.370 33.622 0.000 FLASH 270.000
D89 RECTANGULAR 67.087 55.276 0.000 FLASH 180.000
D90 ROUNDED 57.244 57.244 0.000 FLASH 0.000
D91 RECTANGULAR 34.409 34.409 0.000 FLASH 45.000
D92 RECTANGULAR 34.409 34.409 0.000 FLASH 315.000
D93 RECTANGULAR 51.339 65.118 0.000 FLASH 270.000
D94 ROUNDED 6.667 6.667 0.000 LINE 0.000
D95 ROUNDED 4.000 4.000 0.000 LINE 0.000
D96 ROUNDED 3.937 3.937 0.000 LINE 0.000
D97 ROUNDED 6.000 6.000 0.000 LINE 0.000
D98 ROUNDED 12.598 12.598 0.000 LINE 0.000
D99 ROUNDED 7.874 7.874 0.000 LINE 0.000
Files Generated : 0
Documents Printed : 0
Finished Output Generation At 16:37:45 On 19/10/2010
'altium2gbr v1
setup_fmtype@ 0,1
setup_fmtunit@ 0,0
setup_fmtdigits@ 0,4,4
setunit@ 0
setresolution@ 100
importgbrfile@ 0,0.0000,0.0000,".\EDA-02189-V1-0_ets.gbr"
edit_layer@ 0,10,10,7,0,"ets.gbr"
importgbrfile@ 1,0.0000,0.0000,".\EDA-02189-V1-0_etm.gbr"
edit_layer@ 1,14,14,11,0,"etm.gbr"
importgbrfile@ 2,0.0000,0.0000,".\EDA-02189-V1-0_ltop.gbr"
edit_layer@ 2,2,2,0,0,"ltop.gbr"
importgbrfile@ 3,0.0000,0.0000,".\EDA-02189-V1-0_l2pln.gbr"
edit_layer@ 3,1,1,2,0,"l2pln.gbr"
importgbrfile@ 4,0.0000,0.0000,".\EDA-02189-V1-0_l3.gbr"
edit_layer@ 4,3,3,1,0,"l3.gbr"
importgbrfile@ 5,0.0000,0.0000,".\EDA-02189-V1-0_l4.gbr"
edit_layer@ 5,1,1,1,0,"l4.gbr"
importgbrfile@ 6,0.0000,0.0000,".\EDA-02189-V1-0_l5pln.gbr"
edit_layer@ 6,3,3,2,0,"l5pln.gbr"
importgbrfile@ 7,0.0000,0.0000,".\EDA-02189-V1-0_lbot.gbr"
edit_layer@ 7,0,0,3,0,"lbot.gbr"
importgbrfile@ 8,0.0000,0.0000,".\EDA-02189-V1-0_ebm.gbr"
edit_layer@ 8,12,12,12,0,"ebm.gbr"
importgbrfile@ 9,0.0000,0.0000,".\EDA-02189-V1-0_ebs.gbr"
edit_layer@ 9,6,6,8,0,"ebs.gbr"
importgbrfile@ 10,0.0000,0.0000,".\EDA-02189-V1-0_etp.gbr"
edit_layer@ 10,9,9,19,0,"etp.gbr"
importgbrfile@ 11,0.0000,0.0000,".\EDA-02189-V1-0_ebp.gbr"
edit_layer@ 11,11,11,20,0,"ebp.gbr"
importgbrfile@ 12,0.0000,0.0000,".\EDA-02189-V1-0_etc.gbr"
edit_layer@ 12,4,4,4,0,"etc.gbr"
importgbrfile@ 13,0.0000,0.0000,".\EDA-02189-V1-0_drill-1-6.gbr"
edit_layer@ 13,13,13,4,0,"drill-1-6.gbr"
setlayer@ firstLayer
view_all@
OK_CANCEL "Charger les percages?",OK
if OK = 1 then macro_play ".\load_drills.c3s"
M48
;Layer_Color=0
;FILE_FORMAT=2:4
INCH
;TYPE=NON_PLATED
T14F00S00C0.0374
T15F00S00C0.0512
T16F00S00C0.0610
%
T14
X042756Y039429
X044606
X046575
Y045039
X044606
X042756
X048386Y044122
Y042232
Y040343
T15
X057238Y048718
X058439Y070128
T16
X045945Y040343
Y044122
M30
%FSLAX24Y24*%
%MOIN*%
G70*
G01*
G75*
G04 Layer_Color=16711680*
%ADD10C,0.0500*%
D10*
X52874Y36161D02*
G03*
X52126Y36161I-374J0D01*
G01*
X47717Y37530D02*
G03*
X46280Y37530I-719J0D01*
G01*
X30433Y34983D02*
Y76971D01*
X61024Y33228D02*
X61220Y33425D01*
X53071Y33228D02*
X61024D01*
X61220Y33425D02*
Y38248D01*
X52874Y33425D02*
X53071Y33228D01*
X52874Y33425D02*
Y36161D01*
X51929Y33228D02*
X52126Y33425D01*
X47913Y33228D02*
X51929D01*
X47717Y33425D02*
X47913Y33228D01*
X47717Y33425D02*
Y37530D01*
X46280Y35000D02*
Y37530D01*
X43130Y35000D02*
X46280D01*
X43130D02*
Y38248D01*
X35905D02*
X43130D01*
X52126Y33425D02*
Y36161D01*
X30433Y34983D02*
X35905D01*
Y38248D01*
X61220Y38248D02*
X98025D01*
Y76971D01*
X30433D02*
X98025D01*
M02*
setunit@ 0
nc_add_table@ 3
nc_import_drill_pl@ 14,1,".\EDA-02189-V1-0_drill-1-6.drl"
edit_layer@ 14,12,12,21,0,"drill-1-6"
nc_add_table@ 3
nc_import_drill_upl@ 15,2,".\EDA-02189-V1-0_drill-1-6-np.drl"
edit_layer@ 15,12,12,21,0,"drill-1-6-np"
setlayer@ firstLayer
This source diff could not be displayed because it is too large. You can view the blob instead.
This source diff could not be displayed because it is too large. You can view the blob instead.
Printed Document[EDA-02189-V1-0.pcbdoc]
Files Generated : 0
Documents Printed : 1
Finished Output Generation At 09:05:00 On 19/10/2010
Protel Design System Design Rule Check
PCB File : S:\nlopez\Altium\EDA-02189-V1-0_VANDERBIJ-Simple_PCIe_FMC_Carrier\PCB-Layout\EDA-02189-V1-0.pcbdoc
Date : 19/10/2010
Time : 16:32:10
Processing Rule : Length Constraint (Min=950mil) (Max=1100mil) ((InNet('DDR3_CAS_N') OR InNet('DDR3_UDM') OR InNet('DDR3_LDM') OR InNet('DDR3_UDQS_P') OR InNet('DDR3_UDQS_N') OR InNet('DDR3_LDQS_P') OR InNet('DDR3_LDQS_N') OR InNet('DDR3_CK_N') OR InNet('DDR3_CK_P') OR InNet('DDR3_RAS_N') OR InNet('DDR3_CAS_N') OR
Rule Violations :0
Processing Rule : Length Constraint (Min=950mil) (Max=1100mil) (InNetClass('DDR3_BA[2..0]'))
Rule Violations :0
Processing Rule : Length Constraint (Min=950mil) (Max=1100mil) (InNetClass('DDR3_A[13..0]'))
Rule Violations :0
Processing Rule : Length Constraint (Min=950mil) (Max=1100mil) (InNetClass('DDR3_DQ[15..0]'))
Rule Violations :0
Processing Rule : Room FMC_PCIe_Carrier (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('FMC_PCIe_Carrier'))
Rule Violations :0
Processing Rule : Matched Net Lengths(Tolerance=100mil) (InDifferentialPairClass('PCI_per') or InDifferentialPairClass('C_PCI_pet'))
Rule Violations :0
Processing Rule : Length Constraint (Min=1650mil) (Max=1750mil) ((InDifferentialPairClass('PCI_per')))
Rule Violations :0
Processing Rule : Width Constraint (Min=5mil) (Max=5mil) (Preferred=5mil) ((InDifferentialPairClass('All Differential Pairs')))
Rule Violations :0
Processing Rule : Net Antennae (Tolerance=0mil) (All)
Rule Violations :0
Processing Rule : Silk to Silk (Clearance=1mil) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Silkscreen Over Component Pads (Clearance=1mil) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Minimum Solder Mask Sliver (Gap=1mil) (Disabled)(All),(All)
Rule Violations :0
Processing Rule : Hole To Hole Clearance (Gap=10mil) (All),(All)
Rule Violations :0
Processing Rule : Differential Pairs Uncoupled Length using the Gap Constraints (Min=4.5mil) (Max=5.5mil) (Preferred=5mil) (All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mil) (Max=110.236mil) (Prefered=105mil) (OnBottom)
Rule Violations :0
Processing Rule : Pads and Vias to follow the Drill pairs settings
Rule Violations :0
Processing Rule : Hole Size Constraint (Min=7.874mil) (Max=196.85mil) (All)
Rule Violations :0
Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 10mil ) (All),(All)
Rule Violations :0
Processing Rule : Un-Routed Net Constraint ( (All) )
Rule Violations :0
Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
Rule Violations :0
Processing Rule : Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=15.748mil) (PreferredHoleWidth=11.811mil) (MinWidth=17.716mil) (MaxWidth=31.496mil) (PreferedWidth=23.622mil) (All)
Rule Violations :0
Processing Rule : Power Plane Connect Rule(Direct Connect )(Expansion=5mil) (Conductor Width=5mil) (Air Gap=5mil) (Entries=4) (All)
Rule Violations :0
Processing Rule : Width Constraint (Min=5mil) (Max=100mil) (Preferred=5mil) (All)
Rule Violations :0
Processing Rule : Clearance Constraint (Gap=4mil) (All),(All)
Rule Violations :0
Processing Rule : Height Constraint (Min=0mil) (Max=570mil) (Prefered=570mil) (OnTop)
Rule Violations :0
Processing Rule : Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (InComponentClass('Component_Not_DRC')),(All)
Rule Violations :0
Processing Rule : Length Constraint (Min=1400mil) (Max=1500mil) (InDifferentialPairClass('C_PCI_pet'))
Rule Violations :0
Processing Rule : Room U_clocks (Bounding Region = (7283mil, 7045mil, 7534mil, 7405mil) (Disabled)(InComponentClass('U_clocks'))
Rule Violations :0
Processing Rule : Room U_fmc_connector (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('U_fmc_connector'))
Rule Violations :0
Processing Rule : Room U_fpga_gtp (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('U_fpga_gtp'))
Rule Violations :0
Processing Rule : Room U_fpga_io_bank_0 (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('U_fpga_io_bank_0'))
Rule Violations :0
Processing Rule : Room U_fpga_io_bank_2_fmc (Bounding Region = (0mil, 0mil, 2000mil, 1000mil) (Disabled)(InComponentClass('U_fpga_io_bank_2_fmc'))
Rule Violations