hdl: add generic to bypass gennum core in simulations

8bbdf20f · Tomasz Wlostowski · Federico Vaga · 6289836d · 8bbdf20f
Commit 8bbdf20f authored May 13, 2020 by Tomasz Wlostowski Committed by Federico Vaga May 28, 2020
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Showing with 15 additions and 2 deletions

spec_base_wr.vhd hdl/rtl/spec_base_wr.vhd +15 -2

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--- a/hdl/rtl/spec_base_wr.vhd
+++ b/hdl/rtl/spec_base_wr.vhd
@@ -73,7 +73,8 @@ entity spec_base_wr is
    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
    g_SIMULATION : boolean := False;
    -- Increase information messages during simulation
-    g_VERBOSE    : boolean := False
+    g_VERBOSE    : boolean := False;
+    g_SIM_BYPASS_GENNUM : boolean := False
  );
  port (
    ---------------------------------------------------------------------------
@@ -300,7 +301,10 @@ entity spec_base_wr is
    --  Addresses 0-0x1fff are not available (used by the carrier).
    --  This is a pipelined wishbone with byte granularity.
    app_wb_o           : out t_wishbone_master_out;
-    app_wb_i           : in  t_wishbone_master_in
+    app_wb_i           : in  t_wishbone_master_in;
+
+    sim_wb_i : in t_wishbone_slave_in;
+    sim_wb_o : out t_wishbone_slave_out
  );
 end entity spec_base_wr;

@@ -419,6 +423,8 @@ begin  -- architecture top

  gn_gpio_b(1) <= 'Z';

+  gen_with_gennum : if g_SIMULATION = false or g_sim_bypass_gennum = false generate
+
  cmp_gn4124_core : entity work.xwb_gn4124_core
    generic map (
      g_WITH_DMA                    => g_WITH_DDR,
@@ -502,6 +508,13 @@ begin  -- architecture top
      wb_dma_dat_i       => gn_wb_ddr_in
    );

+  end generate gen_with_gennum;
+
+  gen_without_gennum: if g_SIMULATION = true and g_sim_bypass_gennum = true generate
+    gn_wb_out <= sim_wb_i;
+    sim_wb_o <= gn_wb_in;
+  end generate gen_without_gennum;
+
  --  Mini-crossbar from gennum to carrier and application bus.
  inst_split: entity work.xwb_split
    generic map (