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Simple PCIe FMC carrier SPEC
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Simple PCIe FMC carrier SPEC
Commits
928487bd
Commit
928487bd
authored
Jul 19, 2019
by
Tristan Gingold
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spec template: rename generate stmts.
parent
270ca1d9
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14 deletions
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-14
spec_template_wr.vhd
hdl/rtl/spec_template_wr.vhd
+14
-14
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hdl/rtl/spec_template_wr.vhd
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928487bd
...
...
@@ -541,7 +541,7 @@ begin -- architecture top
end
if
;
end
process
carrier_app_xb
;
i_devs
:
entity
work
.
spec_template_regs
i
nst
_devs
:
entity
work
.
spec_template_regs
port
map
(
rst_n_i
=>
rst_sys_62m5_n
,
clk_i
=>
clk_sys_62m5
,
...
...
@@ -683,7 +683,7 @@ begin -- architecture top
rst_sys_62m5_n_o
<=
rst_sys_62m5_n
and
rst_csr_app_n
;
clk_sys_62m5_o
<=
clk_sys_62m5
;
i_rst_csr_app_sync
:
gc_sync_ffs
i
nst
_rst_csr_app_sync
:
gc_sync_ffs
port
map
(
clk_i
=>
clk_ref_125m
,
rst_n_i
=>
'1'
,
...
...
@@ -693,7 +693,7 @@ begin -- architecture top
rst_ref_125m_n_o
<=
rst_ref_125m_n
and
rst_csr_app_sync_n
;
clk_ref_125m_o
<=
clk_ref_125m
;
i_i2c
:
entity
work
.
xwb_i2c_master
i
nst
_i2c
:
entity
work
.
xwb_i2c_master
generic
map
(
g_interface_mode
=>
CLASSIC
,
g_address_granularity
=>
BYTE
,
...
...
@@ -723,8 +723,8 @@ begin -- architecture top
irqs
(
irq_user_i
'range
)
<=
irq_user_i
;
end
generate
gen_user_irq
;
g_vic
:
if
g_with_vic
generate
i_vic
:
entity
work
.
xwb_vic
g
en
_vic
:
if
g_with_vic
generate
i
nst
_vic
:
entity
work
.
xwb_vic
generic
map
(
g_address_granularity
=>
BYTE
,
g_num_interrupts
=>
num_interrupts
...
...
@@ -739,7 +739,7 @@ begin -- architecture top
);
end
generate
;
g_no_vic
:
if
not
g_with_vic
generate
g
en
_no_vic
:
if
not
g_with_vic
generate
vic_in
<=
(
ack
=>
'1'
,
err
=>
'0'
,
rty
=>
'0'
,
stall
=>
'0'
,
dat
=>
x"00000000"
);
irq_master
<=
'0'
;
end
generate
;
...
...
@@ -751,7 +751,7 @@ begin -- architecture top
-- The WR PTP core board package (WB Slave + WB Master #2 (Etherbone))
-----------------------------------------------------------------------------
g_wr
:
if
g_WITH_WR
generate
g
en
_wr
:
if
g_WITH_WR
generate
-- OneWire
signal
onewire_data
:
std_logic
;
signal
onewire_oe
:
std_logic
;
...
...
@@ -886,7 +886,7 @@ begin -- architecture top
irqs
(
1
)
<=
'0'
;
end
generate
;
g_no_wr
:
if
not
g_WITH_WR
generate
g
en
_no_wr
:
if
not
g_WITH_WR
generate
signal
clk_125m_pllref
:
std_logic
;
signal
pllout_clk_fb_pllref
:
std_logic
;
signal
pllout_clk_62m5
:
std_logic
;
...
...
@@ -975,8 +975,8 @@ begin -- architecture top
wrc_in
<=
(
ack
=>
'1'
,
err
=>
'0'
,
rty
=>
'0'
,
stall
=>
'0'
,
dat
=>
x"00000000"
);
end
generate
;
g_onewire
:
if
g_WITH_ONEWIRE
and
not
g_WITH_WR
generate
i_onewire
:
entity
work
.
xwb_ds182x_readout
g
en
_onewire
:
if
g_WITH_ONEWIRE
and
not
g_WITH_WR
generate
i
nst
_onewire
:
entity
work
.
xwb_ds182x_readout
generic
map
(
g_CLOCK_FREQ_KHZ
=>
62
_
500
,
g_USE_INTERNAL_PPS
=>
True
)
...
...
@@ -992,13 +992,13 @@ begin -- architecture top
);
end
generate
;
g_no_onewire
:
if
not
g_WITH_ONEWIRE
and
not
g_WITH_WR
generate
g
en
_no_onewire
:
if
not
g_WITH_ONEWIRE
and
not
g_WITH_WR
generate
therm_id_in
<=
(
ack
=>
'1'
,
err
=>
'0'
,
rty
=>
'0'
,
stall
=>
'0'
,
dat
=>
x"00000000"
);
onewire_b
<=
'Z'
;
end
generate
;
g_spi
:
if
g_WITH_SPI
and
not
g_WITH_WR
generate
i_spi
:
entity
work
.
xwb_spi
g
en
_spi
:
if
g_WITH_SPI
and
not
g_WITH_WR
generate
i
nst
_spi
:
entity
work
.
xwb_spi
generic
map
(
g_interface_mode
=>
CLASSIC
,
g_address_granularity
=>
BYTE
,
...
...
@@ -1020,7 +1020,7 @@ begin -- architecture top
);
end
generate
;
g_no_spi
:
if
not
g_WITH_SPI
and
not
g_WITH_WR
generate
g
en
_no_spi
:
if
not
g_WITH_SPI
and
not
g_WITH_WR
generate
flash_spi_in
<=
(
ack
=>
'1'
,
err
=>
'0'
,
rty
=>
'0'
,
stall
=>
'0'
,
dat
=>
x"00000000"
);
end
generate
;
...
...
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