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Simple PCIe FMC carrier SPEC
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Simple PCIe FMC carrier SPEC
Commits
b0097d7a
Commit
b0097d7a
authored
Sep 02, 2019
by
Federico Vaga
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Merge remote-tracking branch 'origin/proposed_master' into develop
parents
3e7a6262
778af94f
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Showing
5 changed files
with
140 additions
and
60 deletions
+140
-60
spec_template_wr.vhd
hdl/rtl/spec_template_wr.vhd
+26
-26
Manifest.py
hdl/syn/golden/Manifest.py
+20
-2
syn_extra_steps.tcl
hdl/syn/golden/syn_extra_steps.tcl
+32
-0
Manifest.py
hdl/top/golden/Manifest.py
+1
-1
spec_golden.vhd
hdl/top/golden/spec_golden.vhd
+61
-31
No files found.
hdl/rtl/spec_template_wr.vhd
View file @
b0097d7a
...
...
@@ -80,11 +80,11 @@ entity spec_template_wr is
clk_125m_pllref_n_i
:
in
std_logic
;
-- 20MHz VCXO clock (for WR)
clk_20m_vcxo_i
:
in
std_logic
;
clk_20m_vcxo_i
:
in
std_logic
:
=
'0'
;
-- 125 MHz GTP reference
clk_125m_gtp_n_i
:
in
std_logic
;
clk_125m_gtp_p_i
:
in
std_logic
;
clk_125m_gtp_n_i
:
in
std_logic
:
=
'0'
;
clk_125m_gtp_p_i
:
in
std_logic
:
=
'0'
;
---------------------------------------------------------------------------
-- GN4124 PCIe bridge signals
...
...
@@ -158,13 +158,13 @@ entity spec_template_wr is
-- Green LED next to the SFP: indicates if the link is up.
led_link_o
:
out
std_logic
;
button1_i
:
in
std_logic
;
button1_i
:
in
std_logic
:
=
'1'
;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i
:
in
std_logic
;
uart_rxd_i
:
in
std_logic
:
=
'1'
;
uart_txd_o
:
out
std_logic
;
---------------------------------------------------------------------------
...
...
@@ -182,15 +182,15 @@ entity spec_template_wr is
sfp_txp_o
:
out
std_logic
;
sfp_txn_o
:
out
std_logic
;
sfp_rxp_i
:
in
std_logic
;
sfp_rxn_i
:
in
std_logic
;
sfp_mod_def0_i
:
in
std_logic
;
-- sfp detect
sfp_rxp_i
:
in
std_logic
:
=
'0'
;
sfp_rxn_i
:
in
std_logic
:
=
'0'
;
sfp_mod_def0_i
:
in
std_logic
:
=
'0'
;
-- sfp detect
sfp_mod_def1_b
:
inout
std_logic
;
-- scl
sfp_mod_def2_b
:
inout
std_logic
;
-- sda
sfp_rate_select_o
:
out
std_logic
;
sfp_tx_fault_i
:
in
std_logic
;
sfp_tx_fault_i
:
in
std_logic
:
=
'0'
;
sfp_tx_disable_o
:
out
std_logic
;
sfp_los_i
:
in
std_logic
;
sfp_los_i
:
in
std_logic
:
=
'0'
;
------------------------------------------
-- DDR (bank 3)
...
...
hdl/syn/golden/Manifest.py
View file @
b0097d7a
target
=
"xilinx"
action
=
"synthesis"
fetchto
=
"../../ip_cores"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if
locals
()
.
get
(
'fetchto'
,
None
)
is
None
:
fetchto
=
"../../ip_cores"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
...
...
@@ -10,13 +13,28 @@ syn_project = "spec_golden.xise"
syn_tool
=
"ise"
syn_top
=
"spec_golden"
spec_template_ucf
=
[
'onewire'
,
'spi'
]
board
=
"spec"
ctrls
=
[
"bank3_64b_32b"
]
files
=
[
"buildinfo_pkg.vhd"
]
modules
=
{
"local"
:
[
"../../top/golden"
,
"../../top/golden"
,
"../../syn/common"
],
"git"
:
[
"https://ohwr.org/project/wr-cores.git"
,
"https://ohwr.org/project/general-cores.git"
,
"https://ohwr.org/project/gn4124-core.git"
,
"https://ohwr.org/project/ddr3-sp6-core.git"
,
],
}
# Do not fail during hdlmake fetch
try
:
exec
(
open
(
fetchto
+
"/general-cores/tools/gen_buildinfo.py"
)
.
read
())
except
:
pass
syn_post_project_cmd
=
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/golden/syn_extra_steps.tcl
0 → 100644
View file @
b0097d7a
# get project file from 1st command-line argument
set
project_file
[
lindex
$argv
0
]
if
{
!
[
file
exists
$project
_file
]}
{
report ERROR
"Missing file
$project
_file, exiting."
exit -1
}
xilinx::project open
$project
_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set
"Enable Multi-Threading"
"2"
-process
"Map"
xilinx::project set
"Enable Multi-Threading"
"4"
-process
"Place & Route"
xilinx::project set
"Pack I/O Registers into IOBs"
"Yes"
xilinx::project set
"Pack I/O Registers/Latches into IOBs"
"For Inputs and Outputs"
xilinx::project set
"Register Balancing"
"Yes"
xilinx::project set
"Register Duplication Map"
"On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only
)
" "
Normal
"
xilinx::project save
xilinx::project close
hdl/top/golden/Manifest.py
View file @
b0097d7a
files
=
[
"spec_golden.vhd"
,
"spec_golden.ucf"
]
files
=
[
"spec_golden.vhd"
]
modules
=
{
'local'
:
[
"../../rtl"
]}
hdl/top/golden/spec_golden.vhd
View file @
b0097d7a
...
...
@@ -24,6 +24,7 @@
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
entity
spec_golden
is
port
(
...
...
@@ -64,10 +65,15 @@ entity spec_golden is
gn_TX_ERROR
:
in
std_logic
;
-- Transmit Error
gn_VC_RDY
:
in
std_logic_vector
(
1
downto
0
);
-- Channel ready
-- PCB version
pcbrev_i
:
in
std_logic_vector
(
3
downto
0
);
-- Font panel LEDs
-- LED_RED : out std_logic;
-- LED_GREEN : out std_logic;
button1_i
:
in
std_logic
;
-- I2C to the FMC
fmc0_scl_b
:
inout
std_logic
;
fmc0_sda_b
:
inout
std_logic
;
...
...
@@ -77,9 +83,6 @@ entity spec_golden is
onewire_b
:
inout
std_logic
;
-- button1_i : in std_logic;
-- button2_i : in std_logic;
spi_sclk_o
:
out
std_logic
;
spi_ncs_o
:
out
std_logic
;
spi_mosi_o
:
out
std_logic
;
...
...
@@ -88,38 +91,46 @@ entity spec_golden is
end
spec_golden
;
architecture
rtl
of
spec_golden
is
signal
clk_sys_62m5
:
std_logic
;
signal
rst_sys_62m5_n
:
std_logic
;
signal
gn_wb_out
:
t_wishbone_master_out
;
signal
gn_wb_in
:
t_wishbone_master_in
;
begin
inst_template
:
entity
work
.
spec_template
inst_template
:
entity
work
.
spec_template
_wr
generic
map
(
g_with_vic
=>
true
,
g_with_onewire
=>
true
,
g_with_spi
=>
true
g_WITH_VIC
=>
True
,
g_WITH_ONEWIRE
=>
True
,
g_WITH_SPI
=>
True
,
g_WITH_DDR
=>
False
,
g_WITH_WR
=>
False
,
g_simulation
=>
0
)
port
map
(
clk_125m_pllref_p_i
=>
clk_125m_pllref_p_i
,
clk_125m_pllref_n_i
=>
clk_125m_pllref_n_i
,
gn_rst_n
=>
gn_rst_n
,
gn_
gpio
=>
gn_gpio
,
gn_p2l_
rdy
=>
gn_p2l_rdy
,
gn_p2l_
clk_n
=>
gn_p2l_clk_n
,
gn_p2l_
clk_p
=>
gn_p2l_clk_p
,
gn_p2l_
data
=>
gn_p2l_data
,
gn_p2l_d
frame
=>
gn_p2l_dframe
,
gn_p
2l_valid
=>
gn_p2l_valid
,
gn_p_wr_r
eq
=>
gn_p_wr_req
,
gn_
p_wr_rdy
=>
gn_p_wr_rdy
,
gn_
rx_error
=>
gn_rx_error
,
gn_l2p_
data
=>
gn_l2p_data
,
gn_l2p_dframe
=>
gn_l2p_dframe
,
gn_l2p_valid
=>
gn_l2p_valid
,
gn_l2p_
clk_n
=>
gn_l2p_clk_n
,
gn_l2p_
clk_p
=>
gn_l2p_clk_p
,
gn_l2p_
edb
=>
gn_l2p_edb
,
gn_l
2p_rdy
=>
gn_l2p
_rdy
,
gn_
l_wr_rdy
=>
gn_l_wr
_rdy
,
gn_
p_rd_d_rdy
=>
gn_p_rd_d_rdy
,
gn_
tx_error
=>
gn_tx_error
,
gn_
vc_rdy
=>
gn_vc_rdy
,
gn_rst_n
_i
=>
gn_rst_n
,
gn_
p2l_clk_n_i
=>
gn_p2l_clk_n
,
gn_p2l_
clk_p_i
=>
gn_p2l_clk_p
,
gn_p2l_
rdy_o
=>
gn_p2l_rdy
,
gn_p2l_
dframe_i
=>
gn_p2l_dframe
,
gn_p2l_
valid_i
=>
gn_p2l_valid
,
gn_p2l_d
ata_i
=>
gn_p2l_data
,
gn_p
_wr_req_i
=>
gn_p_wr_req
,
gn_p_wr_r
dy_o
=>
gn_p_wr_rdy
,
gn_
rx_error_o
=>
gn_rx_error
,
gn_
l2p_clk_n_o
=>
gn_l2p_clk_n
,
gn_l2p_
clk_p_o
=>
gn_l2p_clk_p
,
gn_l2p_dframe
_o
=>
gn_l2p_dframe
,
gn_l2p_valid
_o
=>
gn_l2p_valid
,
gn_l2p_
edb_o
=>
gn_l2p_edb
,
gn_l2p_
data_o
=>
gn_l2p_data
,
gn_l2p_
rdy_i
=>
gn_l2p_rdy
,
gn_l
_wr_rdy_i
=>
gn_l_wr
_rdy
,
gn_
p_rd_d_rdy_i
=>
gn_p_rd_d
_rdy
,
gn_
tx_error_i
=>
gn_tx_error
,
gn_
vc_rdy_i
=>
gn_vc_rdy
,
gn_
gpio_b
=>
gn_gpio
,
fmc0_scl_b
=>
fmc0_scl_b
,
fmc0_sda_b
=>
fmc0_sda_b
,
fmc0_prsnt_m2c_n_i
=>
fmc0_prsnt_m2c_n_i
,
...
...
@@ -127,6 +138,25 @@ begin
spi_sclk_o
=>
spi_sclk_o
,
spi_ncs_o
=>
spi_ncs_o
,
spi_mosi_o
=>
spi_mosi_o
,
spi_miso_i
=>
spi_miso_i
spi_miso_i
=>
spi_miso_i
,
pcbrev_i
=>
pcbrev_i
,
ddr_dma_clk_i
=>
clk_sys_62m5
,
ddr_dma_rst_n_i
=>
rst_sys_62m5_n
,
ddr_dma_wb_i
.
cyc
=>
'0'
,
ddr_dma_wb_i
.
stb
=>
'0'
,
ddr_dma_wb_i
.
adr
=>
x"0000_0000"
,
ddr_dma_wb_i
.
sel
=>
x"00"
,
ddr_dma_wb_i
.
we
=>
'0'
,
ddr_dma_wb_i
.
dat
=>
x"0000_0000_0000_0000"
,
ddr_dma_wb_o
=>
open
,
clk_sys_62m5_o
=>
clk_sys_62m5
,
rst_sys_62m5_n_o
=>
rst_sys_62m5_n
,
-- Everything is handled by the carrier.
app_wb_o
=>
gn_wb_out
,
app_wb_i
=>
gn_wb_in
);
gn_wb_in
<=
(
ack
=>
'1'
,
err
|
rty
|
stall
=>
'0'
,
dat
=>
(
others
=>
'0'
));
end
rtl
;
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