Commit caf7d3d9 authored by Matthieu Cattin's avatar Matthieu Cattin

new version of ddr core.

parent 2d11bf03
......@@ -246,6 +246,7 @@ architecture rtl of spec_ddr_test is
component ddr3_ctrl
generic(
g_BANK_PORT_SELECT : string := "BANK3_32B_32B";
g_MEMCLK_PERIOD : integer := 3200; -- in ps
g_SIMULATION : string := "FALSE";
g_CALIB_SOFT_IP : string := "TRUE";
......@@ -712,6 +713,7 @@ begin
------------------------------------------------------------------------------
cmp_ddr_ctrl : ddr3_ctrl
generic map(
g_BANK_PORT_SELECT => "BANK3_32B_32B",
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => g_SIMULATION,
g_CALIB_SOFT_IP => g_CALIB_SOFT_IP,
......
......@@ -581,7 +581,7 @@ TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i_grp" 50 ns HIGH 50%;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/cmp_ddr_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_32b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5" 3.0 ns HIGH 50 %;
......@@ -596,7 +596,7 @@ NET "cmp_gn4124_core/rst_*" TIG;
# DDR3
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/cmp_ddr_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/cmp_ddr_ctrl/c3_pll_lock" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/cmp_ddr_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/cmp_ddr_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_32b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_32b_32b.cmp_ddr3_ctrl/c3_pll_lock" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_32b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_bank3_32b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
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