Commit d624f97d authored by Matthieu Cattin's avatar Matthieu Cattin

Commit of SPEC V2 for schematics and layout review.

parent d4b388ef
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Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_fmc_connector|SchDesignator=U_fmc_connector|FileName=fmc_connector.SchDoc|SymbolType=Normal|RawFileName=fmc_connector.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
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Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_fpga_io_bank_1_PCIe|SchDesignator=U_fpga_io_bank_1_PCIe|FileName=fpga_io_bank_1_PCIe.SchDoc|SymbolType=Normal|RawFileName=fpga_io_bank_1_PCIe.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_fpga_io_bank_2_fmc|SchDesignator=U_fpga_io_bank_2_fmc|FileName=fpga_io_bank_2_fmc.SchDoc|SymbolType=Normal|RawFileName=fpga_io_bank_2_fmc.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_fpga_io_bank_3_ddr3|SchDesignator=U_fpga_io_bank_3_ddr3|FileName=fpga_io_bank_3_ddr3.SchDoc|SymbolType=Normal|RawFileName=fpga_io_bank_3_ddr3.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
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Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_jtga_chain|SchDesignator=U_jtga_chain|FileName=JTAG&CONFIG.SchDoc|SymbolType=Normal|RawFileName=JTAG&CONFIG.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_PCIE_CON|SchDesignator=U_PCIE_CON|FileName=PCIE_CON.SchDoc|SymbolType=Normal|RawFileName=PCIE_CON.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_PCIe_LB_bridge|SchDesignator=U_PCIe_LB_bridge|FileName=PCIe_LB_bridge.SchDoc|SymbolType=Normal|RawFileName=PCIe_LB_bridge.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
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Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_power_supply_linear|SchDesignator=U_power_supply_linear|FileName=power_supply_linear.SchDoc|SymbolType=Normal|RawFileName=power_supply_linear.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_power_supply_switching|SchDesignator=U_power_supply_switching|FileName=power_supply_switching.SchDoc|SymbolType=Normal|RawFileName=power_supply_switching.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_sfp|SchDesignator=U_sfp|FileName=sfp.SchDoc|SymbolType=Normal|RawFileName=sfp.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=SheetSymbol|SourceDocument=FMC_PCIe_Carrier.SchDoc|Designator=U_user_interface|SchDesignator=U_user_interface|FileName=user_interface.SchDoc|SymbolType=Normal|RawFileName=user_interface.SchDoc|DesignItemId= |SourceLibraryName= |ObjectKind=Sheet Symbol
Record=TopLevelDocument|FileName=FMC_PCIe_Carrier.SchDoc
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Files Generated : 0
Documents Printed : 0
Finished Output Generation At 3:31:09 PM On 5/9/2011
Files Generated : 0
Documents Printed : 0
Finished Output Generation At 3:30:57 PM On 5/9/2011
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