Merge branch 'release/v1.4.14'

dfd70891 · Federico Vaga · 6e06f5ba · cd98b268 · dfd70891 · dfd70891
Commit dfd70891 authored May 28, 2020 by Federico Vaga
Showing with 29 additions and 8 deletions

CHANGELOG.rst CHANGELOG.rst +6 -0

spec_base_wr.vhd hdl/rtl/spec_base_wr.vhd +17 -2

spec_base_common.ucf hdl/syn/common/spec_base_common.ucf +2 -2

spec_base_wr.ucf hdl/syn/common/spec_base_wr.ucf +4 -4

No files found.
--- a/CHANGELOG.rst
+++ b/CHANGELOG.rst
@@ -2,6 +2,12 @@
 Changelog
 =========

+[1.4.14] 2020-05-28
+===================
+Added
+-----
+- [hdl] export DDMTD clock output
+
 [1.4.13] 2020-05-12
 ===================
 Fixed

--- a/hdl/rtl/spec_base_wr.vhd
+++ b/hdl/rtl/spec_base_wr.vhd
@@ -73,7 +73,8 @@ entity spec_base_wr is
    -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
    g_SIMULATION : boolean := False;
    -- Increase information messages during simulation
-    g_VERBOSE    : boolean := False
+    g_VERBOSE    : boolean := False;
+    g_SIM_BYPASS_GENNUM : boolean := False
  );
  port (
    ---------------------------------------------------------------------------
@@ -244,6 +245,7 @@ entity spec_base_wr is
    ddr_wr_fifo_empty_o : out std_logic;

    --  Clocks and reset.
+    clk_dmtd_125m_o : out std_logic;
    clk_62m5_sys_o    : out std_logic;
    rst_62m5_sys_n_o  : out std_logic;
    clk_125m_ref_o    : out std_logic;
@@ -299,7 +301,10 @@ entity spec_base_wr is
    --  Addresses 0-0x1fff are not available (used by the carrier).
    --  This is a pipelined wishbone with byte granularity.
    app_wb_o           : out t_wishbone_master_out;
-    app_wb_i           : in  t_wishbone_master_in
+    app_wb_i           : in  t_wishbone_master_in;
+
+    sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
+    sim_wb_o : out t_wishbone_slave_out
  );
 end entity spec_base_wr;

@@ -418,6 +423,8 @@ begin  -- architecture top

  gn_gpio_b(1) <= 'Z';

+  gen_with_gennum : if g_SIMULATION = false or g_sim_bypass_gennum = false generate
+
  cmp_gn4124_core : entity work.xwb_gn4124_core
    generic map (
      g_WITH_DMA                    => g_WITH_DDR,
@@ -501,6 +508,13 @@ begin  -- architecture top
      wb_dma_dat_i       => gn_wb_ddr_in
    );

+  end generate gen_with_gennum;
+
+  gen_without_gennum: if g_SIMULATION = true and g_sim_bypass_gennum = true generate
+    gn_wb_out <= sim_wb_i;
+    sim_wb_o <= gn_wb_in;
+  end generate gen_without_gennum;
+
  --  Mini-crossbar from gennum to carrier and application bus.
  inst_split: entity work.xwb_split
    generic map (
@@ -777,6 +791,7 @@ begin  -- architecture top
        clk_pll_aux_o       => clk_pll_aux,
        rst_sys_62m5_n_o    => rst_62m5_sys_n,
        rst_ref_125m_n_o    => rst_125m_ref_n,
+        clk_dmtd_125m_o     => clk_dmtd_125m_o,
        rst_pll_aux_n_o     => rst_pll_aux_n,

        plldac_sclk_o       => plldac_sclk_o,

--- a/hdl/syn/common/spec_base_common.ucf
+++ b/hdl/syn/common/spec_base_common.ucf
@@ -154,8 +154,8 @@ NET "*/gc_reset_async_in" TIG;

 NET "inst_spec_base/clk_62m5_sys"              TNM_NET = sys_clk;
 NET "inst_spec_base/clk_125m_ref"              TNM_NET = ref_clk;
-NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
-NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/io_clk"  TNM_NET = pci_clk;
+NET "*/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
+NET "*/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/io_clk"  TNM_NET = pci_clk;

 TIMEGRP "sys_grp" = "sys_clk" "ref_clk";


--- a/hdl/syn/common/spec_base_wr.ucf
+++ b/hdl/syn/common/spec_base_wr.ucf
@@ -92,7 +92,7 @@ TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1.25 ns DATAPATHONLY;
 #----------------------------------------

 # Declaration of domains
-NET "*cmp_xwrc_board_spec/clk_pll_dmtd"            TNM_NET = clk_dmtd;
+NET "*cmp_xwrc_board_spec*cmp_dmtd_clk_pll/CLKOUT0"            TNM_NET = clk_dmtd;
 NET "*cmp_xwrc_board_spec/phy8_to_wrc_rx_clk"      TNM_NET = phy_clk;

 TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
@@ -105,9 +105,9 @@ TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
 TIMEGRP "phy_sync_reg"  = "sync_reg" EXCEPT "phy_clk";

 # no gc_sync_reg for DMTD
-#TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
+TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
 TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;

 # no gc_sync_word for DMTD or PHY
-#TIMESPEC TS_dmtd_sync_word = FROM sync_word TO clk_dmtd 48ns DATAPATHONLY;
-#TIMESPEC TS_phy_sync_word  = FROM sync_word TO phy_clk  24ns DATAPATHONLY;
+TIMESPEC TS_dmtd_sync_word = FROM sync_word TO clk_dmtd 48ns DATAPATHONLY;
+TIMESPEC TS_phy_sync_word  = FROM sync_word TO phy_clk  24ns DATAPATHONLY;