Commit f32e834e authored by Greg Daniluk's avatar Greg Daniluk

adding golden FPGA binary

parent caf7d3d9
fetchto = "ip_cores"
modules = {"local" : [ "platform" ],
"git" : "git://ohwr.org/hdl-core-lib/wr-cores.git"
}
modules = {"local" : "xilinx"}
files = [ "wr_xilinx_pkg.vhd" ]
modules = {"local" : ["wr_gtp_phy", "chipscope"]}
\ No newline at end of file
files =["chipscope_icon.ngc", "chipscope_ila.ngc" ]
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files = ["gtp_bitslide.vhd",
"gtp_phase_align.vhd",
"gtp_phase_align_virtex6.vhd",
"gtx_reset.vhd",
"whiterabbitgtx_wrapper_gtx.vhd",
# "whiterabbitgtp_wrapper.vhd",
"whiterabbitgtp_wrapper_tile.vhd",
"wr_gtp_phy_spartan6.vhd",
"wr_gtx_phy_virtex6.vhd"];
-------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - bitslide state machine
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_bitslide.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Module implements a manual bitslide alignment state machine and
-- provides the obtained bitslide value to the MAC.
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN / Tomasz Wlostowski
--
-- <license>
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Ported EASE design to VHDL
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP
-- 2011-09-12 0.6 twlostow Virtex6 port
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtp_bitslide is
generic (
-- set to non-zero value to enable some simulation speedups (reduce delays)
g_simulation : integer;
g_target : string := "spartan6");
port (
gtp_rst_i : in std_logic;
-- GTP
gtp_rx_clk_i : in std_logic;
-- '1' indicates that the GTP has detected a comma in the incoming serial stream
gtp_rx_comma_det_i : in std_logic;
gtp_rx_byte_is_aligned_i : in std_logic;
-- GTP ready flag (PLL locked and RX signal present)
serdes_ready_i : in std_logic;
-- GTP manual bitslip control line
gtp_rx_slide_o : out std_logic;
-- GTP CDR reset, asserted when the link is lost to set the bitslide to a known
-- value
gtp_rx_cdr_rst_o : out std_logic;
-- Current bitslide, in UIs
bitslide_o : out std_logic_vector(4 downto 0);
-- '1' when the bitsliding has been completed and the link is up
synced_o : out std_logic
);
end gtp_bitslide;
architecture behavioral of gtp_bitslide is
function f_eval_sync_detect_threshold
return integer is
begin
if(g_simulation /= 0) then
return 256;
elsif(g_target = "spartan6") then
return 8192;
else
return 16384;
end if;
end f_eval_sync_detect_threshold;
function f_eval_pause_tics return integer is
begin
if(g_target = "spartan6") then
return 31;
else
return 63;
end if;
end f_eval_pause_tics;
constant c_pause_tics : integer := f_eval_pause_tics;
constant c_sync_detect_threshold : integer := f_eval_sync_detect_threshold;
type t_bitslide_fsm_state is (S_SYNC_LOST, S_STABILIZE, S_SLIDE, S_PAUSE, S_GOT_SYNC, S_RESET_CDR);
signal cur_slide : unsigned(4 downto 0);
signal state : t_bitslide_fsm_state;
signal counter : unsigned(15 downto 0);
signal commas_missed : unsigned(1 downto 0);
begin -- behavioral
p_do_slide : process(gtp_rx_clk_i, gtp_rst_i)
begin
if gtp_rst_i = '1' then
state <= S_SYNC_LOST;
gtp_rx_slide_o <= '0';
counter <= (others => '0');
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
elsif rising_edge(gtp_rx_clk_i) then
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
case state is
-- State: synchronization lost. Waits until a comma pattern is detected
when S_SYNC_LOST =>
cur_slide <= (others => '0');
counter <= (others => '0');
gtp_rx_slide_o <= '0';
synced_o <= '0';
gtp_rx_cdr_rst_o <= '0';
commas_missed <= (others => '0');
if(gtp_rx_comma_det_i = '1') then
state <= S_STABILIZE;
end if;
-- State: stabilize:
when S_STABILIZE =>
if(gtp_rx_comma_det_i = '1') then
counter <= counter + 1;
commas_missed <= (others => '0');
else
commas_missed <= commas_missed + 1;
if(commas_missed(1) = '1') then
state <= S_SYNC_LOST;
end if;
end if;
if(counter = to_unsigned(c_sync_detect_threshold, counter'length)) then
counter <= (others => '0');
state <= S_PAUSE;
end if;
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
when S_SLIDE =>
cur_slide <= cur_slide + 1;
gtp_rx_slide_o <= '1';
counter <= (others => '0');
state <= S_PAUSE;
if(serdes_ready_i = '0') then
state <= S_SYNC_LOST;
end if;
when S_PAUSE =>
counter <= counter + 1;
gtp_rx_slide_o <= '0';
if(counter = to_unsigned(c_pause_tics, counter'length)) then
if(gtp_rx_byte_is_aligned_i = '0') then
state <= S_SLIDE;
else
state <= S_GOT_SYNC;
end if;
end if;
when S_GOT_SYNC =>
gtp_rx_slide_o <= '0';
bitslide_o <= std_logic_vector(cur_slide);
synced_o <= '1';
if(gtp_rx_byte_is_aligned_i = '0' or serdes_ready_i = '0') then
gtp_rx_cdr_rst_o <= '1';
state <= S_SYNC_LOST;
end if;
when others => null;
end case;
end if;
end process;
end behavioral;
------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - TX phase alignment
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_phase_align.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: TX phase alignment state machine, as recommended by Xilinx.
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN / Tomasz Wlostowski
--
-- <license>
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Ported EASE design to VHDL
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtp_phase_align is
generic
(g_simulation : integer);
port (
gtp_rst_i : in std_logic;
gtp_tx_clk_i : in std_logic;
gtp_tx_en_pma_phase_align_o : out std_logic;
gtp_tx_pma_set_phase_o : out std_logic;
align_en_i : in std_logic;
align_done_o : out std_logic
);
end gtp_phase_align;
architecture behavioral of gtp_phase_align is
constant c_wait_en_phase_align : integer := 32;
constant c_wait_set_phase_align : integer := 512;
constant c_phase_align_duration : integer := 8192;
type t_align_state is (S_ALIGN_IDLE, S_ALIGN_PAUSE, S_ALIGN_WAIT, S_ALIGN_SET_PHASE, S_ALIGN_DONE);
signal counter : unsigned(13 downto 0);
signal state : t_align_state;
begin -- behavioral
p_align : process(gtp_tx_clk_i, gtp_rst_i)
begin
if rising_edge(gtp_tx_clk_i) then
if gtp_rst_i = '1' then
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
counter <= (others => '0');
align_done_o <= '0';
state <= S_ALIGN_IDLE;
else
if(align_en_i = '0') then
state <= S_ALIGN_IDLE;
else
case (state) is
when S_ALIGN_IDLE =>
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
counter <= (others => '0');
align_done_o <= '0';
if(align_en_i = '1') then
state <= S_ALIGN_PAUSE;
end if;
when S_ALIGN_PAUSE =>
counter <= counter + 1;
if(counter = to_unsigned(c_wait_en_phase_align, counter'length)) then
state <= S_ALIGN_WAIT;
end if;
when S_ALIGN_WAIT =>
gtp_tx_en_pma_phase_align_o <= '1';
counter <= counter + 1;
if(counter = to_unsigned(c_wait_en_phase_align + c_wait_set_phase_align, counter'length)) then
state <= S_ALIGN_SET_PHASE;
end if;
when S_ALIGN_SET_PHASE =>
counter <= counter +1;
gtp_tx_pma_set_phase_o <= '1';
if(counter = to_unsigned(c_wait_en_phase_align + c_wait_set_phase_align + c_phase_align_duration, counter'length)) then
state <= S_ALIGN_DONE;
end if;
when S_ALIGN_DONE =>
gtp_tx_pma_set_phase_o <= '0';
counter <= (others => '0');
align_done_o <= '1';
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
------------------------------------------------------------------------------
-- Title : Deterministic Xilinx GTP wrapper - TX phase alignment
-- Project : White Rabbit Switch
-------------------------------------------------------------------------------
-- File : gtp_phase_align.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2010-11-18
-- Last update: 2011-09-12
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: TX phase alignment state machine, as recommended by Xilinx.
-------------------------------------------------------------------------------
--
-- Original EASE design (c) 2010 NIKHEF / Peter Jansweijer and Henk Peek
-- VHDL port (c) 2010 CERN / Tomasz Wlostowski
--
-- <license>
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2010-11-18 0.4 twlostow Ported EASE design to VHDL
-- 2011-02-07 0.5 twlostow Verified on Spartan6 GTP
-- 2011-09-12 0.6 twlostow Virtex6 port
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtp_phase_align_virtex6 is
generic
(g_simulation : integer);
port (
gtp_rst_i : in std_logic;
gtp_tx_clk_i : in std_logic;
gtp_tx_en_pma_phase_align_o : out std_logic;
gtp_tx_pma_set_phase_o : out std_logic;
gtp_tx_dly_align_disable_o : out std_logic;
gtp_tx_dly_align_reset_o : out std_logic;
align_en_i : in std_logic;
align_done_o : out std_logic
);
end gtp_phase_align_virtex6;
architecture behavioral of gtp_phase_align_virtex6 is
constant c_dly_align_reset_time : integer := 16;
constant c_wait_set_phase_align : integer := 32;
constant c_phase_align_duration : integer := 8192;
type t_align_state is (S_ALIGN_IDLE, S_DLY_ALIGN_RESET, S_ALIGN_WAIT, S_ALIGN_SET_PHASE, S_ALIGN_DONE);
signal counter : unsigned(13 downto 0);
signal state : t_align_state;
begin -- behavioral
p_align : process(gtp_tx_clk_i, gtp_rst_i)
begin
if rising_edge(gtp_tx_clk_i) then
if gtp_rst_i = '1' then
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
gtp_tx_dly_align_reset_o <= '0';
gtp_tx_dly_align_disable_o <= '1';
counter <= (others => '0');
align_done_o <= '0';
state <= S_ALIGN_IDLE;
else
if(align_en_i = '0') then
state <= S_ALIGN_IDLE;
else
case (state) is
when S_ALIGN_IDLE =>
gtp_tx_en_pma_phase_align_o <= '0';
gtp_tx_pma_set_phase_o <= '0';
gtp_tx_dly_align_reset_o <= '0';
gtp_tx_dly_align_disable_o <= '1';
counter <= (others => '0');
align_done_o <= '0';
if(align_en_i = '1') then
state <= S_DLY_ALIGN_RESET;
end if;
when S_DLY_ALIGN_RESET =>
counter <= counter + 1;
gtp_tx_dly_align_reset_o <= '1';
gtp_tx_dly_align_disable_o <= '1';
if(counter = to_unsigned(c_dly_align_reset_time, counter'length)) then
state <= S_ALIGN_WAIT;
end if;
when S_ALIGN_WAIT =>
gtp_tx_dly_align_reset_o <= '0';
gtp_tx_dly_align_disable_o <= '1';
gtp_tx_en_pma_phase_align_o <= '1';
counter <= counter + 1;
if(counter = to_unsigned(c_dly_align_reset_time + c_wait_set_phase_align, counter'length)) then
state <= S_ALIGN_SET_PHASE;
end if;
when S_ALIGN_SET_PHASE =>
counter <= counter +1;
gtp_tx_pma_set_phase_o <= '1';
if(counter = to_unsigned(c_dly_align_reset_time + c_wait_set_phase_align + c_phase_align_duration, counter'length)) then
state <= S_ALIGN_DONE;
end if;
when S_ALIGN_DONE =>
gtp_tx_pma_set_phase_o <= '0';
gtp_tx_dly_align_disable_o <= '0';
counter <= (others => '0');
align_done_o <= '1';
when others => null;
end case;
end if;
end if;
end if;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity gtx_reset is
port (
clk_tx_i : in std_logic;
rst_i : in std_logic;
txpll_lockdet_i : in std_logic;
gtx_test_o : out std_logic_vector(12 downto 0)
);
end gtx_reset;
architecture behavioral of gtx_reset is
type t_state is (IDLE, PAUSE, FIRST_RST, PAUSE2, SECOND_RST, DONE);
signal state : t_state;
signal counter : unsigned(15 downto 0);
begin -- behavioral
process(clk_tx_i)
begin
if rising_edge(clk_tx_i) then
if rst_i = '1' then
state <= IDLE;
counter <= (others => '0');
else
if(txpll_lockdet_i = '0') then
state <= IDLE;
else
case state is
when IDLE =>
counter <= (others => '0');
gtx_test_o <= "1000000000000";
if(txpll_lockdet_i = '1') then
state <= PAUSE;
end if;
when PAUSE =>
counter <= counter + 1;
gtx_test_o <= "1000000000000";
if(counter = 1024) then
state <= FIRST_RST;
end if;
when FIRST_RST =>
counter <= counter + 1;
gtx_test_o <= "1000000000010";
if(counter = 1024 + 256) then
state <= PAUSE2;
end if;
when PAUSE2=>
counter <= counter + 1;
gtx_test_o <= "1000000000000";
if(counter = 1024 + 2*256) then
state <= SECOND_RST;
end if;
when SECOND_RST =>
counter <= counter + 1;
gtx_test_o <= "1000000000010";
if(counter = 1024 + 3*256) then
state <= DONE;
end if;
when DONE =>
gtx_test_o <= "1000000000000";
end case;
end if;
end if;
end if;
end process;
end behavioral;
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library ieee;
use ieee.std_logic_1164.all;
entity wr_gtp_phy_spec_wrapper is
generic (
g_simulation : integer := 0);
port(
sfp_ref_clk_i : in std_logic;
sfp_ref_clk_o : out std_logic;
sfp_tx_data_i : in std_logic_vector(7 downto 0);
sfp_tx_k_i : in std_logic;
sfp_tx_disparity_o : out std_logic;
sfp_tx_enc_err_o : out std_logic;
sfp_rx_rbclk_o : out std_logic;
sfp_rx_data_o : out std_logic_vector(7 downto 0);
sfp_rx_k_o : out std_logic;
sfp_rx_enc_err_o : out std_logic;
sfp_rx_bitslide_o : out std_logic_vector(3 downto 0);
sfp_rst_i : in std_logic;
sfp_loopen_i : in std_logic;
sfp_txn_o : out std_logic;
sfp_txp_o : out std_logic;
sfp_rxn_i : in std_logic;
sfp_rxp_i : in std_logic;
sata0_ref_clk_i : in std_logic;
sata0_ref_clk_o : out std_logic;
sata0_tx_data_i : in std_logic_vector(7 downto 0);
sata0_tx_k_i : in std_logic;
sata0_tx_disparity_o : out std_logic;
sata0_tx_enc_err_o : out std_logic;
sata0_rx_rbclk_o : out std_logic;
sata0_rx_data_o : out std_logic_vector(7 downto 0);
sata0_rx_k_o : out std_logic;
sata0_rx_enc_err_o : out std_logic;
sata0_rx_bitslide_o : out std_logic_vector(3 downto 0);
sata0_rst_i : in std_logic;
sata0_loopen_i : in std_logic;
sata0_txn_o : out std_logic;
sata0_txp_o : out std_logic;
sata0_rxn_i : in std_logic;
sata0_rxp_i : in std_logic;
sata1_ref_clk_i : in std_logic;
sata1_ref_clk_o : out std_logic;
sata1_tx_data_i : in std_logic_vector(7 downto 0);
sata1_tx_k_i : in std_logic;
sata1_tx_disparity_o : out std_logic;
sata1_tx_enc_err_o : out std_logic;
sata1_rx_rbclk_o : out std_logic;
sata1_rx_data_o : out std_logic_vector(7 downto 0);
sata1_rx_k_o : out std_logic;
sata1_rx_enc_err_o : out std_logic;
sata1_rx_bitslide_o : out std_logic_vector(3 downto 0);
sata1_rst_i : in std_logic;
sata1_loopen_i : in std_logic;
sata1_txn_o : out std_logic;
sata1_txp_o : out std_logic;
sata1_rxn_i : in std_logic;
sata1_rxp_i : in std_logic;
fmc_ref_clk_i : in std_logic;
fmc_ref_clk_o : out std_logic;
fmc_tx_data_i : in std_logic_vector(7 downto 0);
fmc_tx_k_i : in std_logic;
fmc_tx_disparity_o : out std_logic;
fmc_tx_enc_err_o : out std_logic;
fmc_rx_rbclk_o : out std_logic;
fmc_rx_data_o : out std_logic_vector(7 downto 0);
fmc_rx_k_o : out std_logic;
fmc_rx_enc_err_o : out std_logic;
fmc_rx_bitslide_o : out std_logic_vector(3 downto 0);
fmc_rst_i : in std_logic;
fmc_loopen_i : in std_logic;
fmc_txn_o : out std_logic;
fmc_txp_o : out std_logic;
fmc_rxn_i : in std_logic;
fmc_rxp_i : in std_logic
);
end wr_gtp_phy_spec_wrapper;
architecture rtl of wr_gtp_phy_spec_wrapper is
component wr_gtp_phy_spartan6
generic (
g_simulation : integer);
port (
ch0_ref_clk_i : in std_logic;
ch0_ref_clk_o : out std_logic;
ch0_tx_data_i : in std_logic_vector(7 downto 0);
ch0_tx_k_i : in std_logic;
ch0_tx_disparity_o : out std_logic;
ch0_tx_enc_err_o : out std_logic;
ch0_rx_rbclk_o : out std_logic;
ch0_rx_data_o : out std_logic_vector(7 downto 0);