Simple PCIe FMC carrier SPEC issueshttps://ohwr.org/project/spec/issues2019-02-12T09:17:57Zhttps://ohwr.org/project/spec/issues/33V4 - Plating of PCIe card edge connector not specified2019-02-12T09:17:57ZErik van der BijV4 - Plating of PCIe card edge connector not specifiedAbout the required gold contacts on the SPEC board:
The PCI express specifications require **0.7um gold over 1.2um nickel**
(PCI express card electromechanical specification rev 2.0, page 78,
below figure 5-5) ([CERN
library](http://cds.cern.ch/record/1247943/files/), CERN only).
It is actually not sure if this is the actual specification for the
thickness. The text is actually about Connector Environmental
Requirements (Durability (mating/unmating) rating of 50 cycles, 7 year
field life) and actually reads:
| To be sure that the environmental tests measure the stability of the
connector, the add-in cards used
shall have edge finger tabs with a minimum plating thickness of 30
microinches of gold over
50 microinches of nickel *for the environmental test purpose* only. |
This amount of gold can be applied using an electrolytic gold plating
method. This is the method for gold plating for the edge connector
contacts. The SPEC design files have all features for this plating
process.
However, the [SPEC manufacturing
specification](https://edms.cern.ch/file/1158536/1/EDA-02189-V4_specif.pdf)
only mentions ENIG gold with a much thinner gold plating specification
despite the fact that the design has been also been made for
electrolytic plating.
| Surface Finish: | ENIG - Electroless Nickel / Immersion Gold according
to IPC-4552 |
| Thicknesses:: | Ni: 3μm min - 6μm max / Au: 0.05μm min - 0.125μm max |
- Add in PCB specification the correct metallisation process and
specification that will arrive at the Environmental Requirements as
specified.
Issue signalled by a subcontractor producing the card.https://ohwr.org/project/spec/issues/30V4 - Space between miniUSB and JTAG connector must increase 1mm2019-02-12T09:17:57ZBenoit RatV4 - Space between miniUSB and JTAG connector must increase 1mmIt is difficult to find a mini-USB cable that can fit in the connector
when the JTAG connector is used.
Adding a space of 1mm between both connector should be enough to correct
this small problems.https://ohwr.org/project/spec/issues/27V4 - PCB revision resistors are set to 3 instead of 4.2019-02-12T09:17:56ZProjectsV4 - PCB revision resistors are set to 3 instead of 4.Change the PCB revision resistors 'mounted' field as follow:
R11 -\> Yes
R21 -\> No
R6 -\> No
R20 -\> Yes
R12 -\> No
R33 -\> Yes
Note: Don't forget to change the comment next to the resistors\!https://ohwr.org/project/spec/issues/24V4 - Serial flash communication issue2019-02-12T09:17:55ZProjectsV4 - Serial flash communication issueDue to the mux (SN74LVC1G97DBVR) and depending on the clock
communication with the M25P32 flash memory might not work as expected.
The mux adds a delay to the clock signal, while the data line from the
memory doesn't have a mux.
As a result the data appear to change a the rising edge instead of the
falling edge of the clock.
See attached presentation extract.
In addition, the data line is floating when the chip is not selected.
Therefore, adding a pull-up/down should be considered.
*This issue has been reported by Magnus Vik Sundal and Heiko Damerau.*
### Files
* [spec_flash_comm.pdf](/uploads/f488454bf6b3385c8c90dc0ee5282d89/spec_flash_comm.pdf)https://ohwr.org/project/spec/issues/23V4 - not compatible PCIe Gen3?2019-02-12T09:17:55ZErik van der BijV4 - not compatible PCIe Gen3?We have heard that the SPEC board does not seem to be detected in
certain modern motherboards. It may be that certain motherboards that
have PCIe Gen 3 slots that are not compatible to the GN4124 that is PCIe
1.1. Apparently PCIe Gen 2 slots work OK.
*We bought a new PC HP Pavillion 500-232d. I tried to setup there my
SPEC plus fine delay. I installed Ubuntu 12.04 LTS with Kernel version
3.11.0-23. However when I plug in my SPEC card and do lspci my spec card
is not shown.*
*We had similar problems with a Supermicro X9SAE-V-4U. It could only
detect the SPEC if there was a single card inserted. As soon as we
inserted another one, both disappeared. We tried all possible
permutations (it has 3 or 4 pcie slots) and BIOS configurations. The
final fix was that we changed to another motherboard.*
Added above text to the [SPEC
FAQ](https://www.ohwr.org/project/spec/wikis/FAQ)https://ohwr.org/project/spec/issues/17V4 - Pull-down resistor on PCIe PERST_N line2023-04-11T14:42:51ZProjectsV4 - Pull-down resistor on PCIe PERST_N lineThe 10k pull-down resistor on PCIe PERST\_N (or PERST\#) line is too low
for certain type of motherboard.
For example, the PCIE-Q57A-R10 Rev 1.0 from IEI is using a 8k2 pull-up
resistor to 3V3 on the PERST\_N line (reposted by Antonin Broquet from
ESRF).
It creates a divider with the 10k on the SPEC, causing the voltage to
drop under Vih\_min (2V) and resetting the GN4124.
The "Gullwing" board (GN4124 evaluation board) uses a 100k pull-down on
PERST\_N.
Perhaps in a future revision, the pull-down should be increased to 100k
on the SPEC.
-----
Here is what the "PCI Express® Card Electromechanical Specification
Revision 2.0" says concerning the PERST\_N line:
$1.5
\> PERST\#, required
$2.2
\> The PERST\# signal is used to indicate when the power supply is
within its specified voltage tolerance and is stable. It also
initializes a component’s state machines and other logic once power
supplies stabilize. On power up, the deassertion of PERST\# is delayed
100 ms (T\_PVPERL) from the power rails achieving specified operating
limits.
\> Also, within this time, the reference clocks 10 (REFCLK+, REFCLK-)
also become stable, at least T\_PERST-CLK before PERST\# is
deasserted.
\> PERST\# is asserted in advance of the power being switched off in a
power-managed state like S3.
\> PERST\# is asserted when the power supply is powered down, but
without the advanced warning of the transition.
$2.6.1
\> Vil\_max = 0.8V
\> Vih\_min = 2.0V
### Files
* [spec_r208.jpg](/uploads/c0da087ad58c0888dd850e2c10c5659d/spec_r208.jpg)https://ohwr.org/project/spec/issues/12V4 - SPI FLASH M25P32-VMF6P End-of-Life2019-08-27T08:43:35ZErik van der BijV4 - SPI FLASH M25P32-VMF6P End-of-LifeThe flash memory M25P32-VMF6P is at End-of-Life.
Find a replacement for new productions.
https://www.micron.com/parts/nor-flash/serial-nor-flash/m25p32-vmf6pba
Thanks to Ronan OGER.
Related to https://www.ohwr.org/work_packages/1539 (CUTE-WR-DP)https://ohwr.org/project/spec/issues/6V4 - SW1 Black jumper not needed2022-11-16T11:04:31ZErik van der BijV4 - SW1 Black jumper not neededThe jumper that is in the BOM does not need to be mounted.
PTS system does not need the jumper to be inserted (on the actual
system. The PTS manual and BOM is wrong). - Verified by Eva and Erik
- Reference: SW1
- Closed Insulated Black Jumper Pitch 2.54mm, CERN SCEM stores
09.55.10.960.9, KONTEK COMATEL 313.1730.0.00.40.0
The PTS manual tells it first needs to be mounted and then to be removed
after the test.
We verified the PTS software that actually tells even before running the
separate test programs that the jumper should *not* be installed.
- Manual of PTS to correct
- BOM to correct
-----
Verified by Eva and Erik.https://ohwr.org/project/spec/issues/3V4 - PCB Hard Gold plating card edge connector not specified2022-11-15T13:41:44ZErik van der BijV4 - PCB Hard Gold plating card edge connector not specifiedIt is not specified in the PCB production documentation that the PCIe
card edge connector needs a Hard Gold plating.
It should have been specified as:
Hard Gold plating on the edge connector fingers, with a thickness of 1.0
μm.
-----
Signalled by two companies that made an offer. Problem never signalled
before for earlier productions.