The main idea underlying this test is comparing two free running clock
domains against the expected values. If the duple of clocks falls in the
validity range, the test is considered successful.
The parameters considered in this test are:
Clock A nominal frequency and stability parameters
Clock B nominal frequency and stability parameters
Number of clock A cycles from a starting point
Number of clock B cycles from a starting point
A hypothetical absolute reference test time
VHDL core: wb_2clock_counter
This is a VHDL core which chains two counters so that the first counter
can stop the count of the second one. Interfacing with the rest of the
FPGA is done via wishbone. The main issue that has been tackled with was
the interface between two different clock domains.
The python program configures the values of the chained wishbone
counters and checks out the values received. Different approaches can be
carried out to test the validity of the results. From a testing
viewpoint, the values that can be studied are:
ASSERTION: Threshold test
In this test the stability parameters are set to a known value.
Consequently, given a nominal frequency and stability parameters of both
clocks known, if we fix the number of cycles in one of the clocks, we
can determine whether the number of cycles in the second is valid or
INFERENCE: Obtaining an estimation of the stability parameters
The aim of the inference test is estimating the stability parameters of
both clocks. To do this, a least squares adjustment is done thanks to
different tests carried out. The tests work by, given a fixed number of
cycles in one of the clocks, batches of tests execute until the fixed
clock runs out. Within these batches, a test set is made up among the
test with same nominal non-free running clock frequency. Thus, by
changing the free-running clock by the non-free-running clock, the
stability parameters can be inferred.
A more detailed explanation of the test can be found here.
How to run the test. Steps!
First we load the firmware: test_clk.bin
Then, we launch the python test program: test_clks.py
An output is obtained in the subfolder: log/test_clk/
---- SPEC V.1.1 Clocks testing ----
-- - - - - - - - - - - - - - - - - - - - - - - --
Test 0 PASS
Test 1 PASS
Test 2 PASS
Test 3 PASS
Test 4 PASS
Test 5 PASS
Test 6 PASS
Test 7 PASS
Test 8 PASS
Test 9 PASS