Skip to content
Simple PCIe FMC carrier SPEC
Create a new issue
Simple PCIe FMC carrier SPEC
Last edited by
Erik van der Bij
Dec 14, 2016
Start of project. Design will be done by an external company, based on the
FMC PCIe Carrier
Reviewing will be done by CERN.
Main features reviewed by JS, PA, MC & EB. Design can start.
First schematics published. Ready for review.
First review held. Considered as a preliminary review as schematics not finished.
Second version schematics published.
Second schematics review held. FMC to Xilinx bank connections not correct.
Clock missing. Supply Xilinx wrong. Cleanup required.
Schematics corrected. Waiting for a final schematics review from CERN.
Third schematics review held.
Review comments integrated
. Start of PCB layout.
PCB layout being made. Will fit on a 6-layer board.
PCB layout 'ready'.
PCB layout modified before review.
Preliminary PCB layout review requiring modifications to layout.
PCB layout review held.
placed for production of three prototypes.
Some final mods to the schematics and PCB. Design passses CERN's design office for standard production files.
Board could not generate interrupts. Found before finalising production files.
Vias designed next to BGA pads which may cause production problems. Needs rework of layout.
Received improved layout. Will pass via CERN's design office.
Design finished. Expect ordered boards by
Production of 3 prototype board finished (see photo above)
Three prototypes arrived at CERN.
Started testing V1
First DDR3 access
WhiteRabbit port GTP transceiver working. Packet Tx/Rx in progress...
Packet transmission and reception works!
All ICs and most slow lines of FMC connector tested. Not yet gigabit lines.
Review of "V1.1" schematics and PCB.
Ordered 10 "V1.1" boards for CERN. Company will produce extra for
Improved version of "V1.1" layout sent for verification by CERN's design office. Planned ready by 29-04-2011.
First V1.1 prototypes received, start testing them.
V1.1 partly tested. Cleaning up schematics for production. Found missing pull-ups.
Review of updated schematics planned to be held on 11-05-2011.
Schematics, layout and production documents for V2 are available in
CERN sent out price enquiry for production of 70 boards. Delivery of pre-series in October.
Sent order for 3 production prototypes.
Demo of production test software shown. Needs only minor modifications.
V2 boards being built.
Three V2 boards received. One fully tested OK. Two only shortly tested.
Modifications for V3 (OHL v1.1, 1 crossover SATA),
Order placed for 70 SPEC cards at Seven Solutions. First batch expected end October.
V3 released. But never built.
V4 released. Solves a minor mechanical problem with the SFP connector.
Pre-production serie of 10 boards was not compliant to IPC-A-610 (Class 2).
11 boards by
7 March. (Update 24-02-2012), another 59 by end April.
CERN accepted the 10 preseries boards that were received on 7 March.
Will receive another 27 cards from Seven Solution by mid-June. And 33 out of the order of 70 later.
SPEC boards passed most restrictive EMC tests for industrial and domestic classes.
CERN ordered 60 cards at INCAA for delivery end September.
Seven Solutions delivered 52 cards. 8 to be delivered later.
Seven Solutions delivered final 8 cards.
CERN entered the modules in the stock for later use in LHC and other accelerators.
60 SPEC boards received from INCAA.
Board available from three commercial producers.
Labview Driver available for
FMC DEL 1ns 4cha
FMC TDC 1ns 5cha
PCIe bridge component (Gennum GN4124) obsolete and not available anymore. A new card should be designed.
Erik van der Bij - 14 December 2016
New Wiki Page
Tip: You can specify the full path for the new file. We will automatically create any missing directories.