Frequently Asked Questions
about the SPEC board
Hardware
Q: The SPEC uses a 4-lane PCIe bus (PCIe x4). Can it work in a x1 slot?
A: The SPEC can work in principle in a x1 slot if it would mechanically fit. Of course it would work only at x1 speed and this is handled fully automatically by the Gennum PCIe interface chip. You can open up the x1 connector on your motherboard (this has been tested on two different systems) or one could cut the SPEC board (we even had foreseen to have no power planes in that area for this purpose). This latter option hasn't been tried out yet.
Q: Do I need to connect the external power supply connector when used in a PCIe slot?
No the power supply is not necessary while connecting through the PCIe slot. The board gets its power from the PCIe card edge connector. This exernal connector is only used in stand-alone applications where the card is not plugged into a PCIe slot.
Q: Does the board comply to CE regulations (EMC)?
A: Yes it does. In June 2012 extensive EMC tests have been performed on
the SPEC with a digital I/O card. These tests have been made by AT4
wireless, a testing laboratory accredited
by the Spanish National Accreditation Body (ENAC -Entidad Nacional de
Acreditación) to perform the tests indicated in the Certificate No.
51/LE 203.
The test report is publicly
available and shows that the card has passed the most restrictive EMC
tests of each class (domestic and industrial) successfully:
- EM Radiated Emission: Class B (Domestic) EN 55022 (2006) / A1 (2007)
- EM Immunity (Industrial): EN 61000-4-3 (2006) / A1 (2008) / A2 (2010), EN 61000-4-4 (2004) / A1 (2010) / Corr (2010), EN 61000-4-6 (2009), EN 61000-4-2 (2009), EN 61000-4-8 (2010).
Q: Is there a users manual available?
A: No, there is not. It would be good to have one, but we just don't
have the time to write it now.
The best starting points are:
- Main features list
- Official production documentation: EDMS EDA-02189 (schematics, PCB layout)
- Software (pointing to examples of the production test software and firmware)
- Gennum GN4124 core bus interface
- Mezzanine projects that use the SPEC as carrier board: fmc-delay-1ns-8cha, fmc-tdc, fmc-adc-100m14b4cha
- Other FAQ questions on this page
Q: The card contains the several oscillators, which ones can I use?
A: the board contains:
- 1x 10-280 MHz I2C Programmable XO Oscillator, starts up at 100 MHz (Silicon Labs Si570, freely usable)
- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- 1x low-jitter frequency synthesizer (TI CDCM61004, fixed configuration, Fout=125 MHz, used by White Rabbit PTP core)
The 25 MHz and 20 MHz ones are used in application using White Rabbit
(see White Rabbit Node Reference
Design).
As White Rabbit is a really nice thing (sub ns synchronisation, data
link to the board, UTC time), I think that you should not try to use
these. Even if you believe right now you don’t need White
Rabbit, you will in the
future
The 25 MHz is used to generate an 125 Mhz clock with the TI CDCM61004.
You may use that clock as the WR core will vary it only by 10 ppm or so.
The Si570 is free for you to use in your application. I don’t believe it is used in our Fine delay, ADC or TDC FMC cards either as these FMC mezzanines have their own local oscillator that feeds it clock from the mezzanine to the carrier. Although it stays programmable, the Si570 that is on the board starts up at 100 MHz.
Firmware
Q: Is there a basic ucf file (all connected IOs and their standards) for the SPECv4?
A: you can use the one we've used for the FmcAdc100M14b4cha:
spec_top_fmc_adc_100Ms.ucf.
You'll just have to rename the signals going to the FMC slot according
to you
needs.
Q: If I use the SPEC in stand-alone mode, can it boot from the SPI Flash memory or do I need a JTAG programmer?
A: In stand-alone mode the Xilinx will boot directly from the SPI Flash
memory (which in turn you must have programmed before with a JTAG
programmer or with an application that programs it via the Gennum PCIe
interface chip).
In applications where the board is used in a Linux PC, the Xilinx will
first load its configuration from the SPI Flash memory with a "golden
firmware" which allows the driver to detect the carrier board type but
also that of the mezzanine. Dependent on that, the driver will then
reconfigure the Xilinx with other, mezzanine (and sometimes application)
dependent software.
Schematics page 10 (V4) describes:
FPGA boot method selection, BOOT_SELx signals are driven by GPIO of the
GN4124. If the GPIO are not configured (high-Z), the pull-up defines the
default mode.
1) From SPI Flash (default mode)
The FPGA is in Master SPI mode and takes its configuration from the SPI
Flash memory.
BOOT_SEL0=high
BOOT_SEL1=high
2) From GN4124
The FPGA is in Slave SPI mode and is configured via the GN4124 by the
driver at startup
BOOT_SEL0=high
BOOT_SEL1=low
3) Access SPI Flash from GN4124
This mode is not used to boot the FPGA, but only to program the SPI
Flash memory from the GN4124.
BOOT_SEL0=low
BOOT_SEL1=low (or high)
Matthieu Cattin, Erik van der Bij - 31 July 2013