-------------------------------------------------------------------------------
-- Title      : WRPC reference design for SPEC7
--            : based on ZYNQ Z030/Z035/Z045
-- Project    : ARM_BASE_SYS
-- URL        : http://empir.npl.co.uk/write/
-------------------------------------------------------------------------------
-- File       : arm_base_sys.vhd
-- Author(s)  : Peter Jansweijer <peterj@nikhef.nl>
-- Company    : Nikhef
-- Created    : 2019-10-09
-- Last update: 2019-10-09
-- Standard   : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the WRPC reference design on the SPEC7
--              in combination with the High Stability external Oscillator.
--              See also EMPIR 17IND14 WRITE Project (http://empir.npl.co.uk/write/)
--
-------------------------------------------------------------------------------
-- Copyright (c) 2019 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE.  See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library work;
library unisim;
use unisim.vcomponents.all;

entity arm_base_sys is
  port (
    MIO                 : INOUT STD_LOGIC_VECTOR(53 DOWNTO 0);
    DDR_CAS_n           : INOUT STD_LOGIC;
    DDR_CKE             : INOUT STD_LOGIC;
    DDR_Clk_n           : INOUT STD_LOGIC;
    DDR_Clk_p           : INOUT STD_LOGIC;
    DDR_CS_n            : INOUT STD_LOGIC;
    DDR_DRSTB           : INOUT STD_LOGIC;
    DDR_ODT             : INOUT STD_LOGIC;
    DDR_RAS_n           : INOUT STD_LOGIC;
    DDR_WEB             : INOUT STD_LOGIC;
    DDR_BankAddr        : INOUT STD_LOGIC_VECTOR(2 DOWNTO 0);
    DDR_Addr            : INOUT STD_LOGIC_VECTOR(14 DOWNTO 0);
    DDR_VRN             : INOUT STD_LOGIC;
    DDR_VRP             : INOUT STD_LOGIC;
    DDR_DM              : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    DDR_DQ              : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
    DDR_DQS_n           : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    DDR_DQS_p           : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    PS_SRSTB            : INOUT STD_LOGIC;
    PS_CLK              : INOUT STD_LOGIC;
    PS_PORB             : INOUT STD_LOGIC;
    leds                : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
  );
end entity arm_base_sys;

architecture top of arm_base_sys is

  -----------------------------------------------------------------------------
  -- Constants
  -----------------------------------------------------------------------------

  -----------------------------------------------------------------------------
  -- Signals
  -----------------------------------------------------------------------------

  component processing_system is
  port (
    DDR_cas_n : inout STD_LOGIC;
    DDR_cke : inout STD_LOGIC;
    DDR_ck_n : inout STD_LOGIC;
    DDR_ck_p : inout STD_LOGIC;
    DDR_cs_n : inout STD_LOGIC;
    DDR_reset_n : inout STD_LOGIC;
    DDR_odt : inout STD_LOGIC;
    DDR_ras_n : inout STD_LOGIC;
    DDR_we_n : inout STD_LOGIC;
    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
    FIXED_IO_ddr_vrn : inout STD_LOGIC;
    FIXED_IO_ddr_vrp : inout STD_LOGIC;
    FIXED_IO_ps_srstb : inout STD_LOGIC;
    FIXED_IO_ps_clk : inout STD_LOGIC;
    FIXED_IO_ps_porb : inout STD_LOGIC;
    gpio_rtl_0_tri_o : out STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  end component processing_system;
begin
  processing_system_i: component processing_system
    port map (
      DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
      DDR_ba(2 downto 0) => DDR_BankAddr(2 downto 0),
      DDR_cas_n => DDR_cas_n,
      DDR_ck_n => DDR_Clk_n,
      DDR_ck_p => DDR_Clk_p,
      DDR_cke => DDR_cke,
      DDR_cs_n => DDR_cs_n,
      DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
      DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
      DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
      DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
      DDR_odt => DDR_odt,
      DDR_ras_n => DDR_ras_n,
      DDR_reset_n => DDR_DRSTB,
      DDR_we_n => DDR_WEB,
      FIXED_IO_ddr_vrn => DDR_VRN,
      FIXED_IO_ddr_vrp => DDR_VRP,
      FIXED_IO_mio(53 downto 0) => MIO(53 downto 0),
      FIXED_IO_ps_clk => PS_CLK,
      FIXED_IO_ps_porb => PS_PORB,
      FIXED_IO_ps_srstb => PS_SRSTB,
      gpio_rtl_0_tri_o => leds(3 downto 0)
    );
end architecture top;
