Frequently Asked Questions
Design
Q: Is the ISERDES also available on the HR pins?
A: Yes.
Q: Why do I get an error "no device detected on target" when using my Xilinx JTAG download cable?
A: SPEC7 switches its JTAG chain between FPGA and Xilinx download cable based on the status of pin 1 of the programmer (see figure 5 of the SPEC7 documentation and/or the schematics sheet 26, J9). Pin 1 is floating on Xilinx Platform Cable USB II (see figure 14) or on the adapter of Digilent JTAG-HS2 hence the JTAG chain on the SPEC7 keeps selecting the default FPGA JTAG pins instead of selecting the download cable JTAG pins.
Solution: You can ground pin 1 by adding a blob of solder between pins 1 and 3 of the download cable connector, see picture below: Cables that do have pin 1 connected are: Xilinx Platform USB and Digilent XUP USB-JTAG programming Cable both referring to the same datasheet (see figure 17).
Gateware compilation
Q: Can I use the free WebPack software?
A: Yes, when the a XC7Z030 is assembled on the board. The Z035 and Z045 are not supported. See on the Xilinx site: Vivado Design Suite Evaluation and WebPACK.
Q: Is partial reconfiguration also available on the WebPack software?
A: No. However, the Partial Reconfiguration feature is also available
for purchase for WebPack
additions.
For example, partial reconfiguration is needed when the SPEC7 needs to
be reconfigured over the PCIe bus.
20 October 2020