hdl/rtl/golden: uploaded missing golden core files

29e8c35b · Tomasz Wlostowski · daf244bf · 29e8c35b · 29e8c35b · 29e8c35b
Commit 29e8c35b authored Feb 04, 2014 by Tomasz Wlostowski
6 changed files
--- a/hdl/rtl/golden/Manifest.py
+++ b/hdl/rtl/golden/Manifest.py
+files = ["golden_core.vhd", "golden_wbgen2_pkg.vhd", "golden_wb.vhd", "golden_core_pkg.vhd"];
--- a/hdl/rtl/golden/golden_core.vhd
+++ b/hdl/rtl/golden/golden_core.vhd
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+use work.wishbone_pkg.all;
+use work.gld_wbgen2_pkg.all;
+
+entity golden_core is
+
+  generic(
+    g_slot_count : integer range 1 to 4);
+  port(
+    clk_sys_i : in std_logic;
+    rst_n_i   : in std_logic;
+
+    slave_i : in  t_wishbone_slave_in;
+    slave_o : out t_wishbone_slave_out;
+
+    fmc_scl_o : out std_logic_vector(g_slot_count-1 downto 0);
+    fmc_sda_o : out std_logic_vector(g_slot_count-1 downto 0);
+
+    fmc_scl_i : in std_logic_vector(g_slot_count-1 downto 0);
+    fmc_sda_i : in std_logic_vector(g_slot_count-1 downto 0);
+
+    fmc_prsnt_n_i : in std_logic_vector(g_slot_count-1 downto 0)
+    );
+
+end golden_core;
+
+architecture rtl of golden_core is
+
+  component golden_wb
+    port (
+      rst_n_i    : in  std_logic;
+      clk_sys_i  : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(2 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      regs_i     : in  t_gld_in_registers;
+      regs_o     : out t_gld_out_registers);
+  end component;
+
+  signal regs_in  : t_gld_in_registers;
+  signal regs_out : t_gld_out_registers;
+  
+begin  -- rtl
+
+  regs_in.csr_slot_count_i <= std_logic_vector(to_unsigned(g_slot_count, 4));
+
+  U_WB_Slave : golden_wb
+    port map (
+      rst_n_i    => rst_n_i,
+      clk_sys_i  => clk_sys_i,
+      wb_adr_i   => slave_i.adr(4 downto 2),
+      wb_dat_i   => slave_i.dat,
+      wb_dat_o   => slave_o.dat,
+      wb_cyc_i   => slave_i.cyc,
+      wb_sel_i   => slave_i.sel,
+      wb_stb_i   => slave_i.stb,
+      wb_we_i    => slave_i.we,
+      wb_ack_o   => slave_o.ack,
+      wb_stall_o => slave_o.stall,
+      regs_i     => regs_in,
+      regs_o     => regs_out);
+
+  gen0 : if(g_slot_count >= 1) generate
+    fmc_scl_o(0)                 <= regs_out.i2cr0_scl_out_o;
+    fmc_sda_o(0)                 <= regs_out.i2cr0_sda_out_o;
+    regs_in.i2cr0_scl_in_i       <= fmc_scl_i(0);
+    regs_in.i2cr0_sda_in_i       <= fmc_sda_i(0);
+    regs_in.csr_fmc_present_i(0) <= not fmc_prsnt_n_i(0);
+  end generate gen0;
+
+  gen1 : if(g_slot_count >= 2) generate
+    fmc_scl_o(1)                 <= regs_out.i2cr1_scl_out_o;
+    fmc_sda_o(1)                 <= regs_out.i2cr1_sda_out_o;
+    regs_in.i2cr1_scl_in_i       <= fmc_scl_i(1);
+    regs_in.i2cr1_sda_in_i       <= fmc_sda_i(1);
+    regs_in.csr_fmc_present_i(1) <= not fmc_prsnt_n_i(1);
+  end generate gen1;
+
+  gen2 : if(g_slot_count >= 3) generate
+    fmc_scl_o(2)                 <= regs_out.i2cr2_scl_out_o;
+    fmc_sda_o(2)                 <= regs_out.i2cr2_sda_out_o;
+    regs_in.i2cr2_scl_in_i       <= fmc_scl_i(2);
+    regs_in.i2cr2_sda_in_i       <= fmc_sda_i(2);
+    regs_in.csr_fmc_present_i(2) <= not fmc_prsnt_n_i(2);
+  end generate gen2;
+
+  gen3 : if(g_slot_count >= 4) generate
+    fmc_scl_o(3)                 <= regs_out.i2cr3_scl_out_o;
+    fmc_sda_o(3)                 <= regs_out.i2cr3_sda_out_o;
+    regs_in.i2cr3_scl_in_i       <= fmc_scl_i(3);
+    regs_in.i2cr3_sda_in_i       <= fmc_sda_i(3);
+    regs_in.csr_fmc_present_i(3) <= not fmc_prsnt_n_i(3);
+  end generate gen3;
+
+end rtl;
--- a/hdl/rtl/golden/golden_core_pkg.vhd
+++ b/hdl/rtl/golden/golden_core_pkg.vhd
+library ieee;
+use ieee.STD_LOGIC_1164.all;
+
+use work.wishbone_pkg.all;
+
+package golden_core_pkg is
+
+  component golden_core
+    generic (
+      g_slot_count : integer range 1 to 4);
+    port (
+      clk_sys_i     : in  std_logic;
+      rst_n_i       : in  std_logic;
+      slave_i       : in  t_wishbone_slave_in;
+      slave_o       : out t_wishbone_slave_out;
+      fmc_scl_o     : out std_logic_vector(g_slot_count-1 downto 0);
+      fmc_sda_o     : out std_logic_vector(g_slot_count-1 downto 0);
+      fmc_scl_i     : in  std_logic_vector(g_slot_count-1 downto 0);
+      fmc_sda_i     : in  std_logic_vector(g_slot_count-1 downto 0);
+      fmc_prsnt_n_i : in  std_logic_vector(g_slot_count-1 downto 0));
+  end component;
+
+  constant c_xwb_golden_sdb : t_sdb_device := (
+    abi_class     => x"0000",              -- undocumented device
+    abi_ver_major => x"01",
+    abi_ver_minor => x"01",
+    wbd_endian    => c_sdb_endian_big,
+    wbd_width     => x"7",                 -- 8/16/32-bit port granularity
+    sdb_component => (
+      addr_first  => x"0000000000000000",
+      addr_last   => x"00000000000000ff",
+      product     => (
+        vendor_id => x"000000000000CE42",  -- CERN
+        device_id => x"676f6c64",
+        version   => x"00000001",
+        date      => x"20130516",
+        name      => "WB-Golden-Core     ")));
+
+end golden_core_pkg;
--- a/hdl/rtl/golden/golden_wb.vhd
+++ b/hdl/rtl/golden/golden_wb.vhd
--- a/hdl/rtl/golden/golden_wb.wb
+++ b/hdl/rtl/golden/golden_wb.wb
+-- -*- Mode: LUA; tab-width: 2 -*-
+
+peripheral {
+   name = "Golden Bitstream WB Slave";
+   description = "A universal Golden Bitstream core for FMC carriers. Supports detection of up to 4 mezzanines";
+   hdl_entity = "golden_wb";
+   prefix = "gld";
+
+   reg {
+      name = "Control/Status reg";
+      prefix = "CSR";
+      field {
+         name = "Number of FMC slots";
+         description = "Number of FMC slots provided by this carrier";
+         prefix = "SLOT_COUNT";
+         type = SLV;
+         size = 4;
+         access_bus = READ_ONLY;
+         access_dev = WRITE_ONLY;
+      };
+
+      field {
+         name = "FMC presence line status";
+         description = "State of presence lines in the respective slots (1 = mezzanine inserted). Bit N = mezzanine (N+1).";
+         prefix = "FMC_PRESENT";
+         type = SLV;
+         size = 4;
+         access_bus = READ_ONLY;
+         access_dev = WRITE_ONLY;
+      };
+   };
+
+   reg {
+      name = "I2C bitbanged IO register for mezzanine 0";
+      prefix = "I2CR0";
+      field {
+         name = "SCL Line out";
+         prefix = "SCL_OUT";
+         type = BIT;
+         reset_value = 1;
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+      };
+      field {
+         name = "SDA Line out";
+         prefix = "SDA_OUT";
+         type = BIT;
+         reset_value = 1;
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+      };
+      field {
+         name = "SCL Line in";
+         prefix = "SCL_IN";
+         type = BIT;
+         access_bus = READ_ONLY;
+         access_dev = WRITE_ONLY;
+      };
+      field {
+         name = "SDA Line in";
+         prefix = "SDA_IN";
+         type = BIT;
+         access_bus = READ_ONLY;
+         access_dev = WRITE_ONLY;
+      };
+   };
+
+   reg {
+      name = "I2C bitbanged IO register for mezzanine 1";
+      prefix = "I2CR1";
+      field {
+         name = "SCL Line out";
+         prefix = "SCL_OUT";
+         type = BIT;
+         reset_value = 1;
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+      };
+      field {
+         name = "SDA Line out";
+         prefix = "SDA_OUT";
+         type = BIT;
+         reset_value = 1;
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+      };
+      field {
+         name = "SCL Line in";
+         prefix = "SCL_IN";
+         type = BIT;
+         access_bus = READ_ONLY;
+         access_dev = WRITE_ONLY;
+      };
+      field {
+         name = "SDA Line in";
+         prefix = "SDA_IN";
+         type = BIT;
+         access_bus = READ_ONLY;
+         access_dev = WRITE_ONLY;
+      };
+   };
+
+   reg {
+      name = "I2C bitbanged IO register for mezzanine 2";
+      prefix = "I2CR2";
+      field {
+         name = "SCL Line out";
+         prefix = "SCL_OUT";
+         type = BIT;
+         reset_value = 1;
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+      };
+      field {
+         name = "SDA Line out";
+         prefix = "SDA_OUT";
+         type = BIT;
+         reset_value = 1;
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+      };
+      field {
+         name = "SCL Line in";
+         prefix = "SCL_IN";
+         type = BIT;
+         access_bus = READ_ONLY;
+         access_dev = WRITE_ONLY;
+      };
+      field {
+         name = "SDA Line in";
+         prefix = "SDA_IN";
+         type = BIT;
+         access_bus = READ_ONLY;
+         access_dev = WRITE_ONLY;
+      };
+   };
+
+   reg {
+      name = "I2C bitbanged IO register for mezzanine 3";
+      prefix = "I2CR3";
+      field {
+         name = "SCL Line out";
+         prefix = "SCL_OUT";
+         type = BIT;
+         reset_value = 1;
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+      };
+      field {
+         name = "SDA Line out";
+         prefix = "SDA_OUT";
+         type = BIT;
+         reset_value = 1;
+         access_bus = READ_WRITE;
+         access_dev = READ_ONLY;
+      };
+      field {
+         name = "SCL Line in";
+         prefix = "SCL_IN";
+         type = BIT;
+         access_bus = READ_ONLY;
+         access_dev = WRITE_ONLY;
+      };
+      field {
+         name = "SDA Line in";
+         prefix = "SDA_IN";
+         type = BIT;
+         access_bus = READ_ONLY;
+         access_dev = WRITE_ONLY;
+      };
+   };
+
+};
\ No newline at end of file
--- a/hdl/rtl/golden/golden_wbgen2_pkg.vhd
+++ b/hdl/rtl/golden/golden_wbgen2_pkg.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Golden Bitstream WB Slave
+---------------------------------------------------------------------------------------
+-- File           : golden_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from golden_wb.wb
+-- Created        : Mon Feb  3 14:32:23 2014
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE golden_wb.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package gld_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_gld_in_registers is record
+    csr_slot_count_i                         : std_logic_vector(3 downto 0);
+    csr_fmc_present_i                        : std_logic_vector(3 downto 0);
+    i2cr0_scl_in_i                           : std_logic;
+    i2cr0_sda_in_i                           : std_logic;
+    i2cr1_scl_in_i                           : std_logic;
+    i2cr1_sda_in_i                           : std_logic;
+    i2cr2_scl_in_i                           : std_logic;
+    i2cr2_sda_in_i                           : std_logic;
+    i2cr3_scl_in_i                           : std_logic;
+    i2cr3_sda_in_i                           : std_logic;
+    end record;
+  
+  constant c_gld_in_registers_init_value: t_gld_in_registers := (
+    csr_slot_count_i => (others => '0'),
+    csr_fmc_present_i => (others => '0'),
+    i2cr0_scl_in_i => '0',
+    i2cr0_sda_in_i => '0',
+    i2cr1_scl_in_i => '0',
+    i2cr1_sda_in_i => '0',
+    i2cr2_scl_in_i => '0',
+    i2cr2_sda_in_i => '0',
+    i2cr3_scl_in_i => '0',
+    i2cr3_sda_in_i => '0'
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_gld_out_registers is record
+      i2cr0_scl_out_o                          : std_logic;
+      i2cr0_sda_out_o                          : std_logic;
+      i2cr1_scl_out_o                          : std_logic;
+      i2cr1_sda_out_o                          : std_logic;
+      i2cr2_scl_out_o                          : std_logic;
+      i2cr2_sda_out_o                          : std_logic;
+      i2cr3_scl_out_o                          : std_logic;
+      i2cr3_sda_out_o                          : std_logic;
+      end record;
+    
+    constant c_gld_out_registers_init_value: t_gld_out_registers := (
+      i2cr0_scl_out_o => '0',
+      i2cr0_sda_out_o => '0',
+      i2cr1_scl_out_o => '0',
+      i2cr1_sda_out_o => '0',
+      i2cr2_scl_out_o => '0',
+      i2cr2_sda_out_o => '0',
+      i2cr3_scl_out_o => '0',
+      i2cr3_sda_out_o => '0'
+      );
+    function "or" (left, right: t_gld_in_registers) return t_gld_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body gld_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_gld_in_registers) return t_gld_in_registers is
+variable tmp: t_gld_in_registers;
+begin
+tmp.csr_slot_count_i := f_x_to_zero(left.csr_slot_count_i) or f_x_to_zero(right.csr_slot_count_i);
+tmp.csr_fmc_present_i := f_x_to_zero(left.csr_fmc_present_i) or f_x_to_zero(right.csr_fmc_present_i);
+tmp.i2cr0_scl_in_i := f_x_to_zero(left.i2cr0_scl_in_i) or f_x_to_zero(right.i2cr0_scl_in_i);
+tmp.i2cr0_sda_in_i := f_x_to_zero(left.i2cr0_sda_in_i) or f_x_to_zero(right.i2cr0_sda_in_i);
+tmp.i2cr1_scl_in_i := f_x_to_zero(left.i2cr1_scl_in_i) or f_x_to_zero(right.i2cr1_scl_in_i);
+tmp.i2cr1_sda_in_i := f_x_to_zero(left.i2cr1_sda_in_i) or f_x_to_zero(right.i2cr1_sda_in_i);
+tmp.i2cr2_scl_in_i := f_x_to_zero(left.i2cr2_scl_in_i) or f_x_to_zero(right.i2cr2_scl_in_i);
+tmp.i2cr2_sda_in_i := f_x_to_zero(left.i2cr2_sda_in_i) or f_x_to_zero(right.i2cr2_sda_in_i);
+tmp.i2cr3_scl_in_i := f_x_to_zero(left.i2cr3_scl_in_i) or f_x_to_zero(right.i2cr3_scl_in_i);
+tmp.i2cr3_sda_in_i := f_x_to_zero(left.i2cr3_sda_in_i) or f_x_to_zero(right.i2cr3_sda_in_i);
+return tmp;
+end function;
+end package body;