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Simple VME FMC Carrier SVEC
Commits
2ffb0319
Commit
2ffb0319
authored
Dec 16, 2019
by
Dimitris Lampridis
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[hdl] fix DDR constraints
parent
9e4d8b96
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4 changed files
with
64 additions
and
61 deletions
+64
-61
CHANGELOG.rst
CHANGELOG.rst
+6
-0
Manifest.py
hdl/syn/common/Manifest.py
+2
-1
svec_base_common.ucf
hdl/syn/common/svec_base_common.ucf
+0
-4
svec_base_ddr5.ucf
hdl/syn/common/svec_base_ddr5.ucf
+56
-56
No files found.
CHANGELOG.rst
View file @
2ffb0319
...
...
@@ -2,6 +2,12 @@
Change Log
==========
[unreleased]
============
Fixed
-----
- [hdl] DDR constraints
[1.4.5] 2019-12-16
==================
Fixed
...
...
hdl/syn/common/Manifest.py
View file @
2ffb0319
...
...
@@ -14,5 +14,6 @@ for p in svec_base_ucf:
f
=
ucf_dict
.
get
(
p
,
None
)
assert
f
is
not
None
,
"unknown name {} in 'svec_base_ucf'"
.
format
(
p
)
if
p
==
'ddr4'
or
p
==
'ddr5'
:
files
.
append
(
'svec_base_ddr_common.ucf'
)
if
'svec_base_ddr_common.ucf'
not
in
files
:
files
.
append
(
'svec_base_ddr_common.ucf'
)
files
.
append
(
f
)
hdl/syn/common/svec_base_common.ucf
View file @
2ffb0319
...
...
@@ -218,10 +218,6 @@ TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_ref" 8 ns HIGH 50%;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
# Ignore async reset to DDR controller
NET "inst_svec_base/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
...
...
hdl/syn/common/svec_base_ddr5.ucf
View file @
2ffb0319
...
...
@@ -14,62 +14,62 @@ NET "ddr5_cke_o" LOC = B29;
NET "ddr5_ck_p_o" LOC = E27;
NET "ddr5_ck_n_o" LOC = E28;
NET "ddr5_cas_n_o" LOC = K27;
NET "ddr5_dq_b[15]"
LOC = M30;
NET "ddr5_dq_b[14]"
LOC = M28;
NET "ddr5_dq_b[13]"
LOC = M27;
NET "ddr5_dq_b[12]"
LOC = M26;
NET "ddr5_dq_b[11]"
LOC = L30;
NET "ddr5_dq_b[10]"
LOC = L29;
NET "ddr5_dq_b[9]"
LOC = L28;
NET "ddr5_dq_b[8]"
LOC = L27;
NET "ddr5_dq_b[7]"
LOC = F30;
NET "ddr5_dq_b[6]"
LOC = F28;
NET "ddr5_dq_b[5]"
LOC = G28;
NET "ddr5_dq_b[4]"
LOC = G27;
NET "ddr5_dq_b[3]"
LOC = G30;
NET "ddr5_dq_b[2]"
LOC = G29;
NET "ddr5_dq_b[1]"
LOC = H30;
NET "ddr5_dq_b[0]"
LOC = H28;
NET "ddr5_ba_o[2]"
LOC = D26;
NET "ddr5_ba_o[1]"
LOC = C27;
NET "ddr5_ba_o[0]"
LOC = D27;
NET "ddr5_a_o[13]"
LOC = A28;
NET "ddr5_a_o[12]"
LOC = B30;
NET "ddr5_a_o[11]"
LOC = A26;
NET "ddr5_a_o[10]"
LOC = F26;
NET "ddr5_a_o[9]"
LOC = A27;
NET "ddr5_a_o[8]"
LOC = B27;
NET "ddr5_a_o[7]"
LOC = C29;
NET "ddr5_a_o[6]"
LOC = H27;
NET "ddr5_a_o[5]"
LOC = H26;
NET "ddr5_a_o[4]"
LOC = F27;
NET "ddr5_a_o[3]"
LOC = E29;
NET "ddr5_a_o[2]"
LOC = C30;
NET "ddr5_a_o[1]"
LOC = D30;
NET "ddr5_a_o[0]"
LOC = D28;
NET "ddr5_dq_b[15]" LOC = M30;
NET "ddr5_dq_b[14]" LOC = M28;
NET "ddr5_dq_b[13]" LOC = M27;
NET "ddr5_dq_b[12]" LOC = M26;
NET "ddr5_dq_b[11]" LOC = L30;
NET "ddr5_dq_b[10]" LOC = L29;
NET "ddr5_dq_b[9]" LOC = L28;
NET "ddr5_dq_b[8]" LOC = L27;
NET "ddr5_dq_b[7]" LOC = F30;
NET "ddr5_dq_b[6]" LOC = F28;
NET "ddr5_dq_b[5]" LOC = G28;
NET "ddr5_dq_b[4]" LOC = G27;
NET "ddr5_dq_b[3]" LOC = G30;
NET "ddr5_dq_b[2]" LOC = G29;
NET "ddr5_dq_b[1]" LOC = H30;
NET "ddr5_dq_b[0]" LOC = H28;
NET "ddr5_ba_o[2]" LOC = D26;
NET "ddr5_ba_o[1]" LOC = C27;
NET "ddr5_ba_o[0]" LOC = D27;
NET "ddr5_a_o[13]" LOC = A28;
NET "ddr5_a_o[12]" LOC = B30;
NET "ddr5_a_o[11]" LOC = A26;
NET "ddr5_a_o[10]" LOC = F26;
NET "ddr5_a_o[9]" LOC = A27;
NET "ddr5_a_o[8]" LOC = B27;
NET "ddr5_a_o[7]" LOC = C29;
NET "ddr5_a_o[6]" LOC = H27;
NET "ddr5_a_o[5]" LOC = H26;
NET "ddr5_a_o[4]" LOC = F27;
NET "ddr5_a_o[3]" LOC = E29;
NET "ddr5_a_o[2]" LOC = C30;
NET "ddr5_a_o[1]" LOC = D30;
NET "ddr5_a_o[0]" LOC = D28;
# DDR IO standards and terminations
NET "ddr5_udqs_p_b
[*]
" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_udqs_n_b
[*]
" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ldqs_p_b
[*]
" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ldqs_n_b
[*]
" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ck_p_o
[*]
" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ck_n_o
[*]
" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_rzq_b
[*]
" IOSTANDARD = "SSTL15_II";
NET "ddr5_we_n_o
[*]
" IOSTANDARD = "SSTL15_II";
NET "ddr5_udm_o
[*]
" IOSTANDARD = "SSTL15_II";
NET "ddr5_reset_n_o
[*]
" IOSTANDARD = "SSTL15_II";
NET "ddr5_ras_n_o
[*]
" IOSTANDARD = "SSTL15_II";
NET "ddr5_odt_o
[*]
" IOSTANDARD = "SSTL15_II";
NET "ddr5_ldm_o
[*]
" IOSTANDARD = "SSTL15_II";
NET "ddr5_cke_o
[*]
" IOSTANDARD = "SSTL15_II";
NET "ddr5_cas_n_o
[*]
" IOSTANDARD = "SSTL15_II";
NET "ddr5_dq_b[*]"
IOSTANDARD = "SSTL15_II";
NET "ddr5_ba_o[*]"
IOSTANDARD = "SSTL15_II";
NET "ddr5_a_o[*]"
IOSTANDARD = "SSTL15_II";
NET "ddr5_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr5_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr5_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr5_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr5_dq_b[*]"
IN_TERM = NONE;
NET "ddr5_ldqs_p_b
[*]
" IN_TERM = NONE;
NET "ddr5_ldqs_n_b
[*]
" IN_TERM = NONE;
NET "ddr5_udqs_p_b
[*]
" IN_TERM = NONE;
NET "ddr5_udqs_n_b
[*]
" IN_TERM = NONE;
NET "ddr5_dq_b[*]" IN_TERM = NONE;
NET "ddr5_ldqs_p_b" IN_TERM = NONE;
NET "ddr5_ldqs_n_b" IN_TERM = NONE;
NET "ddr5_udqs_p_b" IN_TERM = NONE;
NET "ddr5_udqs_n_b" IN_TERM = NONE;
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