Commit 347107a6 authored by Tristan Gingold's avatar Tristan Gingold

svec_vmecore_test_top: update comments for PLL.

parent b41bd58c
......@@ -7,7 +7,7 @@
-- Author(s) : Tristan Gingold <tristan.gingold@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-09-19
-- Last update: 2017-11-27
-- Last update: 2017-12-05
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the test design .
......@@ -242,10 +242,10 @@ begin -- architecture top
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50, -- 1Ghz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8, -- 62.5 MHz
CLKOUT0_DIVIDE => 8, -- 2*62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 62.5 MHz
CLKOUT1_DIVIDE => 8, -- 2*62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment