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Simple VME FMC Carrier SVEC
Commit 3da89c5c authored by Tristan Gingold's avatar Tristan Gingold
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svec golden wr: fix port names, connexions... Tested ok.

parent bcf5473e
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Showing with 10 additions and 13 deletions
hdl/syn/golden_wr/Manifest.py
View file @ 3da89c5c
...@@ -23,7 +23,8 @@ files = [ "buildinfo_pkg.vhd" ] ...@@ -23,7 +23,8 @@ files = [ "buildinfo_pkg.vhd" ]
modules = { modules = {
"local" : [ "local" : [
"../../top/golden_wr", "../../top/golden_wr",
], "../../syn/common",
],
"git" : [ "git" : [
"https://ohwr.org/project/wr-cores.git", "https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git", "https://ohwr.org/project/general-cores.git",
......
hdl/top/golden_wr/svec_golden_wr.vhd
View file @ 3da89c5c
...@@ -134,8 +134,6 @@ entity svec_golden_wr is ...@@ -134,8 +134,6 @@ entity svec_golden_wr is
plldac_sclk_o : out std_logic; plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic; plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
pll20dac_din_o : out std_logic; pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic; pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic; pll20dac_sync_n_o : out std_logic;
...@@ -190,10 +188,10 @@ entity svec_golden_wr is ...@@ -190,10 +188,10 @@ entity svec_golden_wr is
fp_led_column_o : out std_logic_vector(3 downto 0); fp_led_column_o : out std_logic_vector(3 downto 0);
-- GPIO -- GPIO
fp_gpio1_o : out std_logic; -- PPS output fp_gpio1_b : out std_logic; -- PPS output
fp_gpio2_o : out std_logic; -- not used fp_gpio2_b : out std_logic; -- not used
fp_gpio3_o : out std_logic; -- not used fp_gpio3_b : out std_logic; -- not used
fp_gpio4_o : out std_logic; -- not used fp_gpio4_b : out std_logic; -- not used
fp_term_en_o : out std_logic_vector(4 downto 1); fp_term_en_o : out std_logic_vector(4 downto 1);
fp_gpio1_a2b_o : out std_logic; fp_gpio1_a2b_o : out std_logic;
fp_gpio2_a2b_o : out std_logic; fp_gpio2_a2b_o : out std_logic;
...@@ -284,8 +282,6 @@ begin ...@@ -284,8 +282,6 @@ begin
uart_txd_o => uart_txd_o, uart_txd_o => uart_txd_o,
plldac_sclk_o => plldac_sclk_o, plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o, plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
pll20dac_din_o => pll20dac_din_o, pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o, pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o, pll20dac_sync_n_o => pll20dac_sync_n_o,
...@@ -441,10 +437,10 @@ begin ...@@ -441,10 +437,10 @@ begin
led_state(15 downto 14) <= c_led_red_green when wr_led_act = '1' else c_led_off; led_state(15 downto 14) <= c_led_red_green when wr_led_act = '1' else c_led_off;
-- Front panel IO configuration -- Front panel IO configuration
fp_gpio1_o <= pps_p; fp_gpio1_b <= pps_p;
fp_gpio2_o <= '0'; fp_gpio2_b <= '0';
fp_gpio3_o <= '0'; fp_gpio3_b <= '0';
fp_gpio4_o <= '0'; fp_gpio4_b <= '0';
fp_term_en_o <= (others => '0'); fp_term_en_o <= (others => '0');
fp_gpio1_a2b_o <= '1'; fp_gpio1_a2b_o <= '1';
fp_gpio2_a2b_o <= '1'; fp_gpio2_a2b_o <= '1';
......
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