Commit 41415b81 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

svec_base_wr: added DDMTD clock output

parent cf6b2894
......@@ -92,6 +92,7 @@ entity svec_base_wr is
clk_125m_gtp_n_i : in std_logic := '0';
clk_125m_gtp_p_i : in std_logic := '0';
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_AUX_CLKS-1 downto 0) := (others => '0');
......@@ -268,6 +269,9 @@ entity svec_base_wr is
clk_ref_125m_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
-- 125 MHz DDMTD clock output
clk_dmtd_125m_o : out std_logic;
-- Interrupts
irq_user_i : in std_logic_vector(g_NUM_USER_IRQ + 5 downto 6) := (others => '0');
......@@ -448,11 +452,13 @@ architecture top of svec_base_wr is
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
signal clk_dmtd_125m : std_logic;
attribute keep : string;
attribute keep of clk_sys_62m5 : signal is "TRUE";
attribute keep of clk_ref_125m : signal is "TRUE";
attribute keep of clk_ddr_333m : signal is "TRUE";
attribute keep of ddr_rst : signal is "TRUE";
attribute keep of ddr_rst : signal is "TRUE";
begin -- architecture top
......@@ -798,6 +804,7 @@ begin -- architecture top
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
clk_pll_aux_o => clk_pll_aux,
clk_dmtd_125m_o => clk_dmtd_125m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
rst_pll_aux_n_o => rst_pll_aux_n,
......@@ -1220,5 +1227,7 @@ begin -- architecture top
-- TODO
ddr5_wb_out <= (adr => (others => 'X'), cyc => '0', stb => '0', sel => x"0", we => '0',
dat => (others => 'X'));
dat => (others => 'X'));
clk_dmtd_125m_o <= clk_dmtd_125m;
end architecture top;
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