Commit 549f475e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

doc: few words on gensdbfs

parent 8d75dee4
......@@ -194,7 +194,7 @@ Only A32/A24/D32/CSR address modifiers are supported.
The SVEC Application FPGA can be programmed with the @code{svec-flasher} tool, located in @code{software/vme-flasher} subdirectory of the SVEC project repository. It requires a @code{.bin} format bitstream, that can be generated by Xilinx ISE by selecting ``Generate binary configuration file'' in @i{Generate Programming File} options.
The flasher requires the slot number as the first argument and the file with the bitstream as the second, just like in the example below:
@smallexample
@example
# ./svec-flasher.L865 12 /lib/firmware/fmc/svec-golden.bin
Programming the Application FPGA flash with bitstream /lib/firmware/fmc/svec-golden.bin.
Programming page 7651/7651.
......@@ -202,12 +202,12 @@ Verification...
Programming page 0/0.
Verification...
Programming OK.
@end smallexample
@end example
@b{Note 1:} Before programming the flash, please unload the SVEC kernel driver:
@smallexample
@example
# rmmod svec
@end smallexample
@end example
@b{Note 2:} The flasher must be run as root.
@b{Note 3:} The card must be rebooted for the new bitstream to start working.
......@@ -241,6 +241,21 @@ Preparing the flash image is straightforward:
@item Program the Flash (@code{image.mcs}) via iMPACT, using the procedure described in the previous section.
@end itemize
The script requires the @code{gensdbfs} utility. The easiest way to install it is to:
@itemize
@item Clone the @code{fpga-config-space} repository:
@example
git clone git://ohwr.org/hdl-core-lib/fpga-config-space.git.
@end example
@item Compile it:
@example
cd fpga-config-space/sdbfs/lib
make
cd ../userspace
make
@end example
@item Copy @code{gensdbfs} binary to a directory within the @code{PATH}.
@end itemize
@page
@chapter References
......
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