@@ -194,7 +194,7 @@ Only A32/A24/D32/CSR address modifiers are supported.
The SVEC Application FPGA can be programmed with the @code{svec-flasher} tool, located in @code{software/vme-flasher} subdirectory of the SVEC project repository. It requires a @code{.bin} format bitstream, that can be generated by Xilinx ISE by selecting ``Generate binary configuration file'' in @i{Generate Programming File} options.
The flasher requires the slot number as the first argument and the file with the bitstream as the second, just like in the example below: