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Simple VME FMC Carrier SVEC
Commits
6a0da397
Commit
6a0da397
authored
Jan 16, 2014
by
Tomasz Wlostowski
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sim,testbench: uploaded missing files
parent
7f4f97a4
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7 changed files
with
298 additions
and
113 deletions
+298
-113
golden_regs.vh
hdl/sim/regs/golden_regs.vh
+41
-0
sxldr_regs.vh
hdl/sim/regs/sxldr_regs.vh
+2
-0
vme64x_bfm.svh
hdl/sim/vme64x_bfm/vme64x_bfm.svh
+2
-2
main.sv
hdl/testbench/golden/main.sv
+42
-9
wave.do
hdl/testbench/golden/wave.do
+137
-71
main.sv
hdl/testbench/sfpga_bootloader/main.sv
+9
-3
wave.do
hdl/testbench/sfpga_bootloader/wave.do
+65
-28
No files found.
hdl/sim/regs/golden_regs.vh
0 → 100644
View file @
6a0da397
`define ADDR_GLD_CSR 5'h0
`define GLD_CSR_SLOT_COUNT_OFFSET 0
`define GLD_CSR_SLOT_COUNT 32'h0000000f
`define GLD_CSR_FMC_PRESENT_OFFSET 4
`define GLD_CSR_FMC_PRESENT 32'h000000f0
`define ADDR_GLD_I2CR0 5'h4
`define GLD_I2CR0_SCL_OUT_OFFSET 0
`define GLD_I2CR0_SCL_OUT 32'h00000001
`define GLD_I2CR0_SDA_OUT_OFFSET 1
`define GLD_I2CR0_SDA_OUT 32'h00000002
`define GLD_I2CR0_SCL_IN_OFFSET 2
`define GLD_I2CR0_SCL_IN 32'h00000004
`define GLD_I2CR0_SDA_IN_OFFSET 3
`define GLD_I2CR0_SDA_IN 32'h00000008
`define ADDR_GLD_I2CR1 5'h8
`define GLD_I2CR1_SCL_OUT_OFFSET 0
`define GLD_I2CR1_SCL_OUT 32'h00000001
`define GLD_I2CR1_SDA_OUT_OFFSET 1
`define GLD_I2CR1_SDA_OUT 32'h00000002
`define GLD_I2CR1_SCL_IN_OFFSET 2
`define GLD_I2CR1_SCL_IN 32'h00000004
`define GLD_I2CR1_SDA_IN_OFFSET 3
`define GLD_I2CR1_SDA_IN 32'h00000008
`define ADDR_GLD_I2CR2 5'hc
`define GLD_I2CR2_SCL_OUT_OFFSET 0
`define GLD_I2CR2_SCL_OUT 32'h00000001
`define GLD_I2CR2_SDA_OUT_OFFSET 1
`define GLD_I2CR2_SDA_OUT 32'h00000002
`define GLD_I2CR2_SCL_IN_OFFSET 2
`define GLD_I2CR2_SCL_IN 32'h00000004
`define GLD_I2CR2_SDA_IN_OFFSET 3
`define GLD_I2CR2_SDA_IN 32'h00000008
`define ADDR_GLD_I2CR3 5'h10
`define GLD_I2CR3_SCL_OUT_OFFSET 0
`define GLD_I2CR3_SCL_OUT 32'h00000001
`define GLD_I2CR3_SDA_OUT_OFFSET 1
`define GLD_I2CR3_SDA_OUT 32'h00000002
`define GLD_I2CR3_SCL_IN_OFFSET 2
`define GLD_I2CR3_SCL_IN 32'h00000004
`define GLD_I2CR3_SDA_IN_OFFSET 3
`define GLD_I2CR3_SDA_IN 32'h00000008
hdl/sim/regs/sxldr_regs.vh
View file @
6a0da397
...
...
@@ -15,6 +15,8 @@
`define SXLDR_CSR_EXIT 32'h00000040
`define SXLDR_CSR_CLKDIV_OFFSET 8
`define SXLDR_CSR_CLKDIV 32'h00003f00
`define SXLDR_CSR_VERSION_OFFSET 14
`define SXLDR_CSR_VERSION 32'h003fc000
`define ADDR_SXLDR_BTRIGR 5'h4
`define ADDR_SXLDR_FAR 5'h8
`define SXLDR_FAR_DATA_OFFSET 0
...
...
hdl/sim/vme64x_bfm/vme64x_bfm.svh
View file @
6a0da397
...
...
@@ -250,9 +250,9 @@ class CBusAccessor_VME64x extends CBusAccessor;
A16:
a_out
=
{
16'h0
,
m_ba
[
7
:
3
]
,
a
[
10
:
2
]
,
2'b00
};
A24:
a_out
=
{
8'h0
,
m_ba
[
7
:
3
]
,
a
[
18
:
2
]
,
2'b00
};
a_out
=
{
8'h0
,
a
[
23
:
2
]
,
2'b00
};
A32:
a_out
=
{
m_ba
[
7
:
3
]
,
a
[
26
:
2
]
,
2'b00
};
a_out
=
{
a
[
31
:
2
]
,
2'b00
};
endcase
// case (xtype)
vme
.
q_addr
[
31
:
2
]
=
a_out
[
31
:
2
]
;
...
...
hdl/testbench/golden/main.sv
View file @
6a0da397
`include
"vme64x_bfm.svh"
`include
"svec_vme_buffers.svh"
`include
"../regs/golden_regs.vh"
module
main
;
...
...
@@ -26,20 +27,35 @@ module main;
`WIRE_VME_PINS
(
8
)
)
;
task
automatic
config_vme_function
(
ref
CBusAccessor_VME64x
acc
,
input
int
func
,
uint64_t
base
,
int
am
)
;
uint64_t
addr
=
'h7ff63
+
func
*
'h10
;
uint64_t
val
=
(
base
)
|
(
am
<<
2
)
;
$
display
(
"Func%d ADER=0x%x"
,
func
,
val
)
;
acc
.
write
(
addr
+
0
,
(
val
>>
24
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
addr
+
4
,
(
val
>>
16
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
addr
+
8
,
(
val
>>
8
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
addr
+
12
,
(
val
>>
0
)
&
'hff
,
CR_CSR
|
A32
|
D08Byte3
)
;
endtask
// config_vme_function
task
automatic
init_vme64x_core
(
ref
CBusAccessor_VME64x
acc
)
;
uint64_t
rv
;
/* map func0 to 0x80000000, A32 */
config_vme_function
(
acc
,
0
,
'h80000000
,
'h09
)
;
/* map func1 to 0xc00000, A24 */
config_vme_function
(
acc
,
1
,
'hc00000
,
'h39
)
;
acc
.
write
(
'h7ff63
,
'h80
,
A32
|
CR_CSR
|
D08Byte3
)
;
acc
.
write
(
'h7ff67
,
0
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff6b
,
0
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff6f
,
36
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7ff33
,
1
,
CR_CSR
|
A32
|
D08Byte3
)
;
acc
.
write
(
'h7fffb
,
'h10
,
CR_CSR
|
A32
|
D08Byte3
)
;
/* enable module (BIT_SET = 0x10) */
acc
.
set_default_modifiers
(
A32
|
D32
|
SINGLE
)
;
acc
.
set_default_modifiers
(
A24
|
D32
|
SINGLE
)
;
endtask
// init_vme64x_core
...
...
@@ -55,9 +71,26 @@ module main;
init_vme64x_core
(
acc
)
;
acc
.
read
(
0
,
d
,
A32
|
SINGLE
|
D32
)
;
// acc.read('h80000000, d, A32|SINGLE|D32);
// $display("Read0: %x\n", d);
$
display
(
"pre-read"
)
;
acc
.
read
(
'hc00000
,
d
,
A24
|
SINGLE
|
D32
)
;
$
display
(
"Read0: %x
\n
"
,
d
)
;
acc
.
read
(
'h80000000
,
d
,
A32
|
SINGLE
|
D32
)
;
$
display
(
"Read1: %x
\n
"
,
d
)
;
/*
acc.write('h80010000, d, A24|SINGLE|D32);
acc.read('h80010000, d, A24|SINGLE|D32);
acc.write('h80010000 + `ADDR_GLD_I2CR0, ~`GLD_I2CR0_SCL_OUT, A24|SINGLE|D32);
acc.write('h80010000 + `ADDR_GLD_I2CR0, ~`GLD_I2CR0_SDA_OUT, A24|SINGLE|D32);
acc.write('h810000 + `ADDR_GLD_I2CR1, ~`GLD_I2CR0_SCL_OUT, A24|SINGLE|D32);
acc.write('h810000 + `ADDR_GLD_I2CR1, ~`GLD_I2CR0_SDA_OUT, A24|SINGLE|D32);
$display("Read1: %x\n", d);
*/
end
...
...
hdl/testbench/golden/wave.do
View file @
6a0da397
This diff is collapsed.
Click to expand it.
hdl/testbench/sfpga_bootloader/main.sv
View file @
6a0da397
...
...
@@ -33,7 +33,7 @@ module main;
always
#
25
ns
clk_20m
<=
~
clk_20m
;
initial
begin
repeat
(
1
0000
)
@
(
posedge
clk_20m
)
;
repeat
(
2
0000
)
@
(
posedge
clk_20m
)
;
rst_n
=
1
;
end
...
...
@@ -80,7 +80,7 @@ module main;
M25Pxxx
Flash
(
.
S
(
spi_cs
)
,
.
C
(
spi_sclk
)
,
.
HOLD
(
1'b1
)
,
.
D
(
spi_mosi
)
,
.
Q
(
spi_miso
)
,
.
Vpp_W
(
32'h0
)
,
.
Vcc
(
32'd3000
))
;
parameter
[
12
*
8
:
1
]
mem
=
"../../../software/sdb-flash/image.vmf"
;
parameter
[
12
8
*
8
:
1
]
mem
=
"../../../software/sdb-flash/image.vmf"
;
defparam
Flash
.
memory_file
=
mem
;
class
CSimDrv_Xloader
;
...
...
@@ -140,6 +140,10 @@ class CSimDrv_Xloader;
acc
.
write
(
base
+
`ADDR_SXLDR_BTRIGR
,
boot_seq
[
i
])
;
endtask
// enter_boot_mode
task
exit_boot_mode
()
;
acc
.
write
(
base
+
`ADDR_SXLDR_CSR
,
`SXLDR_CSR_EXIT
)
;
endtask
// enter_boot_mode
task
load_bitstream
(
string
filename
)
;
int
f
,
i
,
pos
=
0
;
...
...
@@ -206,7 +210,7 @@ endclass
#
6
00u
s
;
#
11
00u
s
;
acc
.
set_default_modifiers
(
A32
|
CR_CSR
|
D32
)
;
drv
=
new
(
acc
,
'h70000
)
;
...
...
@@ -222,6 +226,8 @@ endclass
$
display
(
"Flash ID: %02x %02x %02x
\n
"
,
payload
[
0
]
,
payload
[
1
]
,
payload
[
2
])
;
drv
.
exit_boot_mode
()
;
// drv.load_bitstream("sample_bitstream/crc_gen.bin");
...
...
hdl/testbench/sfpga_bootloader/wave.do
View file @
6a0da397
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/enable_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/clk_sys_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/rst_n_i
add wave -noupdate -radix hexadecimal -expand -subitemconfig {/main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.csr_start_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.csr_msbf_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.csr_swrst_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.csr_exit_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.csr_clkdiv_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.btrigr_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.btrigr_wr_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.gpior_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.fifo_rd_full_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.fifo_rd_empty_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.fifo_xsize_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.fifo_xlast_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.fifo_xdata_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.far_data_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.far_data_load_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.far_xfer_o {-height 17 -radix hexadecimal} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i.far_cs_o {-height 17 -radix hexadecimal}} /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/regs_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/set_addr_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/addr_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/read_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/data_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/ready_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_cs_n_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_sclk_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_mosi_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_miso_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_cs
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_cs_muxed
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_start
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_start_host
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_start_muxed
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_wdata
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_wdata_host
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_wdata_muxed
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_rdata
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/spi_ready
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/state
add wave -noupdate -radix hexadecimal /main/DUT/U_Bootloader_Core/U_Flash_Boot_Engine/U_Flash_Controller/ready_int
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/clk_sys_i
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/rst_vme_n_a_i
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/rst_local_n_a_i
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/rst_n_o
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/powerup_cnt
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/local_synced_n
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/vme_synced_n
add wave -noupdate -expand -group Pwr-rst /main/DUT/U_Powerup_Reset/powerup_n
add wave -noupdate /main/DUT/lclk_n_i
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/VME_AS_n_i
add wave -noupdate /main/DUT/VME_RST_n_i
add wave -noupdate /main/DUT/VME_WRITE_n_i
add wave -noupdate /main/DUT/VME_AM_i
add wave -noupdate /main/DUT/VME_DS_n_i
add wave -noupdate /main/DUT/VME_GA_i
add wave -noupdate /main/DUT/VME_DTACK_n_o
add wave -noupdate /main/DUT/VME_LWORD_n_b
add wave -noupdate /main/DUT/VME_ADDR_b
add wave -noupdate /main/DUT/VME_DATA_b
add wave -noupdate /main/DUT/VME_DTACK_OE_o
add wave -noupdate /main/DUT/VME_DATA_DIR_o
add wave -noupdate /main/DUT/VME_DATA_OE_N_o
add wave -noupdate /main/DUT/VME_ADDR_DIR_o
add wave -noupdate /main/DUT/VME_ADDR_OE_N_o
add wave -noupdate /main/DUT/VME_BBSY_n_i
add wave -noupdate /main/DUT/boot_clk_o
add wave -noupdate /main/DUT/boot_config_o
add wave -noupdate /main/DUT/boot_done_i
add wave -noupdate /main/DUT/boot_dout_o
add wave -noupdate /main/DUT/boot_status_i
add wave -noupdate /main/DUT/spi_cs_n_o
add wave -noupdate /main/DUT/spi_mosi_o
add wave -noupdate /main/DUT/spi_miso_i
add wave -noupdate /main/DUT/spi_sclk_o
add wave -noupdate /main/DUT/debugled_o
add wave -noupdate /main/DUT/pll_ce_o
add wave -noupdate /main/DUT/VME_DATA_o_int
add wave -noupdate /main/DUT/vme_dtack_oe_int
add wave -noupdate /main/DUT/VME_DTACK_n_int
add wave -noupdate /main/DUT/vme_data_dir_int
add wave -noupdate /main/DUT/VME_DATA_OE_N_int
add wave -noupdate /main/DUT/wb_vme_in
add wave -noupdate /main/DUT/wb_vme_out
add wave -noupdate /main/DUT/passive
add wave -noupdate /main/DUT/boot_en
add wave -noupdate /main/DUT/boot_trig_p1
add wave -noupdate /main/DUT/boot_exit_p1
add wave -noupdate /main/DUT/CONTROL
add wave -noupdate /main/DUT/CLK
add wave -noupdate /main/DUT/TRIG0
add wave -noupdate /main/DUT/TRIG1
add wave -noupdate /main/DUT/TRIG2
add wave -noupdate /main/DUT/TRIG3
add wave -noupdate /main/DUT/boot_config_int
add wave -noupdate /main/DUT/erase_afpga_n
add wave -noupdate /main/DUT/erase_afpga_n_d0
add wave -noupdate /main/DUT/pllout_clk_fb_sys
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/clk_sys
add wave -noupdate /main/DUT/rst_n_sys
add wave -noupdate /main/DUT/go_passive
add wave -noupdate /main/DUT/vme_idle
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {
729769000
ps} 0}
WaveRestoreCursors {{Cursor 1} {
2145098
ps} 0}
configure wave -namecolwidth 177
configure wave -valuecolwidth 100
configure wave -justifyvalue left
...
...
@@ -42,4 +79,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {
446436072 ps} {101142192
8 ps}
WaveRestoreZoom {
0 ps} {1765580
8 ps}
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