Commit 90348ce2 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

svec7: test project

parent 41415b81
files = [
"../svec_base_regs.vhd",
"svec7_base_wr.vhd",
"litedram_core.v"
]
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target = "xilinx"
action = "synthesis"
syn_device = "xc7k325t"
syn_grade = "-2"
syn_package = "ffg900"
syn_top = "svec7_test_top"
syn_project = "svec7_test_top"
syn_tool = "vivado"
include_dirs=[ "../../../../vme64x-core/hdl/sim/vme64x_bfm",
"../../../../general-cores/sim",
"../../../../general-cores/modules/wishbone/wb_spi",
"../../../../general-cores/modules/wishbone/wb_lm32/src",
"." ]
modules = {
"local" : [ "../../rtl/svec7",
"../../top/svec7_test",
"../../../../wr-cores",
"../../../../general-cores",
"../../../../vme64x-core"
],
}
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action = "simulation"
target = "xilinx"
sim_tool = "modelsim"
sim_top = "main"
vcom_opt = "-93 -mixedsvvh"
syn_device = "xc7k325t"
svec_template_ucf = []
board = "svec7"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
include_dirs=[ "../../../../vme64x-core/hdl/sim/vme64x_bfm",
"../../../../general-cores/sim",
"../../../../general-cores/modules/wishbone/wb_spi",
"../../../../general-cores/modules/wishbone/wb_lm32/src",
"." ]
files = [ "main.sv", "buildinfo_pkg.vhd" ]
modules = {
"local" : [ "../../rtl/svec7",
"../../top/svec7_test",
"../../../../wr-cores",
"../../../../general-cores",
"../../../../vme64x-core"
],
}
# Do not fail during hdlmake fetch
try:
exec(open("../../../../general-cores/tools/gen_buildinfo.py").read())
except:
pass
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
import wishbone_pkg::*;
module main;
reg rst_n = 0;
reg clk_125m_pllref = 0;
wire clk_62m5;
wire rst_62m5_n;
initial begin
repeat(20) @(posedge clk_125m_pllref);
rst_n = 1;
end
// 125Mhz
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
IVME64X VME(rst_n);
`DECLARE_VME_BUFFERS(VME.slave);
logic ddr_reset_n;
logic ddr_ck_p;
logic ddr_ck_n;
logic ddr_cke;
logic ddr_ras_n;
logic ddr_cas_n;
logic ddr_we_n;
wire [7:0] ddr_dm;
logic [2:0] ddr_ba;
logic [14:0] ddr_a;
wire [63:0] ddr_dq;
wire [7:0] ddr_dqs_p;
wire [7:0] ddr_dqs_n;
wire ddr_rzq;
logic ddr_odt;
logic [4:0] slot_id = 5'h8;
svec7_test_top
#(
.g_SIMULATION(1'b1)
)
DUT (
.rst_n_i(rst_n),
.clk_62m5_pllref_p_i (clk_125m_pllref),
.clk_62m5_pllref_n_i (~clk_125m_pllref),
.clk_20m_vcxo_i (1'b0),
.clk_125m_gtx_n_i (1'b0),
.clk_125m_gtx_p_i (1'b1),
.vme_as_n_i (VME_AS_n),
.vme_sysreset_n_i (VME_RST_n),
.vme_write_n_i (VME_WRITE_n),
.vme_am_i (VME_AM),
.vme_ds_n_i (VME_DS_n),
.vme_gap_i (^slot_id),
.vme_ga_i (~slot_id),
.vme_berr_o (VME_BERR),
.vme_dtack_n_o (VME_DTACK_n),
.vme_retry_n_o (VME_RETRY_n),
.vme_retry_oe_o (VME_RETRY_OE),
.vme_lword_n_b (VME_LWORD_n),
.vme_addr_b (VME_ADDR),
.vme_data_b (VME_DATA),
.vme_irq_o (VME_IRQ_n),
.vme_iack_n_i (VME_IACK_n),
.vme_iackin_n_i (VME_IACKIN_n),
.vme_iackout_n_o (VME_IACKOUT_n),
.vme_dtack_oe_o (VME_DTACK_OE),
.vme_data_dir_o (VME_DATA_DIR),
.vme_data_oe_n_o (VME_DATA_OE_N),
.vme_addr_dir_o (VME_ADDR_DIR),
.vme_addr_oe_n_o (VME_ADDR_OE_N),
.fmc0_scl_b (),
.fmc0_sda_b (),
.fmc1_scl_b (),
.fmc1_sda_b (),
.fmc0_prsnt_m2c_n_i (),
.fmc1_prsnt_m2c_n_i (),
.onewire_b (),
.carrier_scl_b (),
.carrier_sda_b (),
// .spi_sclk_o (),
.spi_ncs_o (),
.spi_mosi_o (),
.spi_miso_i (),
.uart_rxd_i (),
.uart_txd_o (),
.pll20dac_din_o (),
.pll20dac_sclk_o (),
.pll20dac_sync_n_o (),
.pll25dac_din_o (),
.pll25dac_sclk_o (),
.pll25dac_sync_n_o (),
.sfp_txp_o (),
.sfp_txn_o (),
.sfp_rxp_i (),
.sfp_rxn_i (),
.sfp_mod_def0_i (),
.sfp_mod_def1_b (),
.sfp_mod_def2_b (),
.sfp_rate_select_o (),
.sfp_tx_fault_i (),
.sfp_tx_disable_o (),
.sfp_los_i (),
.ddr_a_o (ddr_a),
.ddr_ba_o (ddr_ba),
.ddr_cas_n_o (ddr_cas_n),
.ddr_ck_p_o (ddr_ck_p),
.ddr_ck_n_o (ddr_ck_n),
.ddr_cke_o (ddr_cke),
.ddr_dq_b (ddr_dq),
.ddr_odt_o (ddr_odt),
.ddr_ras_n_o (ddr_ras_n),
.ddr_reset_n_o (ddr_reset_n),
.ddr_rzq_b (ddr_rzq),
.ddr_dm_o (ddr_dm),
.ddr_dqs_n_b (ddr_dqs_n),
.ddr_dqs_p_b (ddr_dqs_p),
.ddr_we_n_o (ddr_we_n),
.ddr_cs_n_o (ddr_cs_n),
.pcbrev_i (5'h2)
);
/* -----\/----- EXCLUDED -----\/-----
ddr3
cmp_ddr4 (
.rst_n (ddr_reset_n),
.ck (ddr_ck_p),
.ck_n (ddr_ck_n),
.cke (ddr_cke),
.cs_n (1'b0),
.ras_n (ddr_ras_n),
.cas_n (ddr_cas_n),
.we_n (ddr_we_n),
.dm_tdqs ({ddr_dm[1], ddr_dm[0]}),
.ba (ddr_ba),
.addr (ddr_a),
.dq (ddr_dq),
.dqs ({ddr_dqs_p[1],ddr_dqs_p[0]}),
.dqs_n ({ddr_dqs_n[1],ddr_dqs_n[0]}),
.odt (ddr_odt),
.tdqs_n ()
);
-----/\----- EXCLUDED -----/\----- */
task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
uint64_t rv;
/* map func0 to 0x80000000, A32 */
acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
acc.set_default_modifiers(A32 | D32 | SINGLE);
endtask // init_vme64x_core
initial begin
uint64_t d;
int i, result;
automatic CBusAccessor_VME64x acc = new(VME.tb);
// automatic CWishboneAccessor ddr4_acc = xwb_ddr4.get_accessor();
#1us;
init_vme64x_core(acc);
// Display meta data
for (i = 0; i < 8'h20; i += 4)
begin
acc.read('h80000000 | i, d, A32|SINGLE|D32);
$display("Read %x: %x", i, d);
end
acc.read('h80000050, d, A32|SINGLE|D32);
$display("ddr status: %x", d);
// Write ddr4
// ddr4_acc.set_mode(PIPELINED);
// ddr4_acc.write(0, 64'h1122334455667788, 8);
// Read DDR4
acc.read('h80000000 | 8'h5c, d, A32|SINGLE|D32);
$display("Read data: %08x", d);
acc.read('h80000000 | 8'h58, d, A32|SINGLE|D32);
$display("Read addr: %x", d);
acc.read('h80000000 | 8'h5c, d, A32|SINGLE|D32);
$display("Read data: %08x", d);
acc.read('h80000000 | 8'h58, d, A32|SINGLE|D32);
$display("Read addr: %x", d);
/*
acc.write('h80010000, d, A24|SINGLE|D32);
acc.read('h80010000, d, A24|SINGLE|D32);
acc.write('h80010000 + `ADDR_GLD_I2CR0, ~`GLD_I2CR0_SCL_OUT, A24|SINGLE|D32);
acc.write('h80010000 + `ADDR_GLD_I2CR0, ~`GLD_I2CR0_SDA_OUT, A24|SINGLE|D32);
acc.write('h810000 + `ADDR_GLD_I2CR1, ~`GLD_I2CR0_SCL_OUT, A24|SINGLE|D32);
acc.write('h810000 + `ADDR_GLD_I2CR1, ~`GLD_I2CR0_SDA_OUT, A24|SINGLE|D32);
$display("Read1: %x\n", d);
*/
end
endmodule // main
vsim -quiet -t 10fs -L unisim work.main -novopt
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
log -r /*
run 1us
wave zoomfull
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/rst_n_i
add wave -noupdate /main/DUT/clk_20m_vcxo_i
add wave -noupdate /main/DUT/clk_62m5_pllref_p_i
add wave -noupdate /main/DUT/clk_62m5_pllref_n_i
add wave -noupdate /main/DUT/clk_125m_gtx_n_i
add wave -noupdate /main/DUT/clk_125m_gtx_p_i
add wave -noupdate /main/DUT/clk_fpga2_p_i
add wave -noupdate /main/DUT/clk_fpga2_n_i
add wave -noupdate /main/DUT/clk_si57x_p_i
add wave -noupdate /main/DUT/clk_si57x_n_i
add wave -noupdate /main/DUT/vme_write_n_i
add wave -noupdate /main/DUT/vme_sysreset_n_i
add wave -noupdate /main/DUT/vme_retry_oe_o
add wave -noupdate /main/DUT/vme_retry_n_o
add wave -noupdate /main/DUT/vme_lword_n_b
add wave -noupdate /main/DUT/vme_iackout_n_o
add wave -noupdate /main/DUT/vme_iackin_n_i
add wave -noupdate /main/DUT/vme_iack_n_i
add wave -noupdate /main/DUT/vme_gap_i
add wave -noupdate /main/DUT/vme_dtack_oe_o
add wave -noupdate /main/DUT/vme_dtack_n_o
add wave -noupdate /main/DUT/vme_ds_n_i
add wave -noupdate /main/DUT/vme_data_oe_n_o
add wave -noupdate /main/DUT/vme_data_dir_o
add wave -noupdate /main/DUT/vme_berr_o
add wave -noupdate /main/DUT/vme_as_n_i
add wave -noupdate /main/DUT/vme_addr_oe_n_o
add wave -noupdate /main/DUT/vme_addr_dir_o
add wave -noupdate /main/DUT/vme_irq_o
add wave -noupdate /main/DUT/vme_ga_i
add wave -noupdate /main/DUT/vme_data_b
add wave -noupdate /main/DUT/vme_am_i
add wave -noupdate /main/DUT/vme_addr_b
add wave -noupdate /main/DUT/vme_noga_i
add wave -noupdate /main/DUT/vme_use_ga_i
add wave -noupdate /main/DUT/pll20dac_din_o
add wave -noupdate /main/DUT/pll20dac_sclk_o
add wave -noupdate /main/DUT/pll20dac_sync_n_o
add wave -noupdate /main/DUT/pll25dac_din_o
add wave -noupdate /main/DUT/pll25dac_sclk_o
add wave -noupdate /main/DUT/pll25dac_sync_n_o
add wave -noupdate /main/DUT/sfp_txp_o
add wave -noupdate /main/DUT/sfp_txn_o
add wave -noupdate /main/DUT/sfp_rxp_i
add wave -noupdate /main/DUT/sfp_rxn_i
add wave -noupdate /main/DUT/sfp_mod_def0_i
add wave -noupdate /main/DUT/sfp_mod_def1_b
add wave -noupdate /main/DUT/sfp_mod_def2_b
add wave -noupdate /main/DUT/sfp_rate_select_o
add wave -noupdate /main/DUT/sfp_tx_fault_i
add wave -noupdate /main/DUT/sfp_tx_disable_o
add wave -noupdate /main/DUT/sfp_los_i
add wave -noupdate /main/DUT/carrier_scl_b
add wave -noupdate /main/DUT/carrier_sda_b
add wave -noupdate /main/DUT/pcbrev_i
add wave -noupdate /main/DUT/onewire_b
add wave -noupdate /main/DUT/uart_rxd_i
add wave -noupdate /main/DUT/uart_txd_o
add wave -noupdate /main/DUT/spi_ncs_o
add wave -noupdate /main/DUT/spi_mosi_o
add wave -noupdate /main/DUT/spi_miso_i
add wave -noupdate /main/DUT/fp_led_line_oen_o
add wave -noupdate /main/DUT/fp_led_line_o
add wave -noupdate /main/DUT/fp_led_column_o
add wave -noupdate /main/DUT/fp_gpio1_b
add wave -noupdate /main/DUT/fp_gpio2_b
add wave -noupdate /main/DUT/fp_gpio3_b
add wave -noupdate /main/DUT/fp_gpio4_b
add wave -noupdate /main/DUT/fp_term_en_o
add wave -noupdate /main/DUT/fp_gpio1_a2b_o
add wave -noupdate /main/DUT/fp_gpio2_a2b_o
add wave -noupdate /main/DUT/fp_gpio34_a2b_o
add wave -noupdate /main/DUT/fp_pushbutton_n_i
add wave -noupdate /main/DUT/fmc0_la_p_b
add wave -noupdate /main/DUT/fmc0_la_n_b
add wave -noupdate /main/DUT/fmc0_pg_i
add wave -noupdate /main/DUT/fmc0_prsnt_m2c_n_i
add wave -noupdate /main/DUT/fmc0_clk_m2c_p_i
add wave -noupdate /main/DUT/fmc0_clk_m2c_n_i
add wave -noupdate /main/DUT/fmc0_scl_b
add wave -noupdate /main/DUT/fmc0_sda_b
add wave -noupdate /main/DUT/fmc0_tck_o
add wave -noupdate /main/DUT/fmc0_tms_o
add wave -noupdate /main/DUT/fmc0_tdi_o
add wave -noupdate /main/DUT/fmc0_tdo_i
add wave -noupdate /main/DUT/fmc1_la_p_b
add wave -noupdate /main/DUT/fmc1_la_n_b
add wave -noupdate /main/DUT/fmc1_pg_i
add wave -noupdate /main/DUT/fmc1_prsnt_m2c_n_i
add wave -noupdate /main/DUT/fmc1_clk_m2c_p_i
add wave -noupdate /main/DUT/fmc1_clk_m2c_n_i
add wave -noupdate /main/DUT/fmc1_scl_b
add wave -noupdate /main/DUT/fmc1_sda_b
add wave -noupdate /main/DUT/fmc1_tck_o
add wave -noupdate /main/DUT/fmc1_tms_o
add wave -noupdate /main/DUT/fmc1_tdi_o
add wave -noupdate /main/DUT/fmc1_tdo_i
add wave -noupdate /main/DUT/p2_p_b
add wave -noupdate /main/DUT/p2_n_b
add wave -noupdate /main/DUT/ddr_a_o
add wave -noupdate /main/DUT/ddr_ba_o
add wave -noupdate /main/DUT/ddr_cas_n_o
add wave -noupdate /main/DUT/ddr_ck_n_o
add wave -noupdate /main/DUT/ddr_ck_p_o
add wave -noupdate /main/DUT/ddr_cke_o
add wave -noupdate /main/DUT/ddr_dq_b
add wave -noupdate /main/DUT/ddr_ldm_o
add wave -noupdate /main/DUT/ddr_dqs_n_b
add wave -noupdate /main/DUT/ddr_dqs_p_b
add wave -noupdate /main/DUT/ddr_odt_o
add wave -noupdate /main/DUT/ddr_ras_n_o
add wave -noupdate /main/DUT/ddr_reset_n_o
add wave -noupdate /main/DUT/ddr_rzq_b
add wave -noupdate /main/DUT/ddr_dm_o
add wave -noupdate /main/DUT/ddr_we_n_o
add wave -noupdate /main/DUT/ddr_cs_n_o
add wave -noupdate /main/DUT/si57x_scl_b
add wave -noupdate /main/DUT/si57x_sda_b
add wave -noupdate /main/DUT/si57x_oe_o
add wave -noupdate /main/DUT/si57x_tune_o
add wave -noupdate /main/DUT/cnx_master_out
add wave -noupdate /main/DUT/cnx_master_in
add wave -noupdate /main/DUT/cnx_slave_out
add wave -noupdate /main/DUT/cnx_slave_in
add wave -noupdate /main/DUT/areset_n
add wave -noupdate /main/DUT/clk_sys_62m5
add wave -noupdate /main/DUT/rst_sys_62m5_n
add wave -noupdate /main/DUT/clk_ref_62m5
add wave -noupdate /main/DUT/clk_ext_ref
add wave -noupdate /main/DUT/eeprom_sda_in
add wave -noupdate /main/DUT/eeprom_sda_out
add wave -noupdate /main/DUT/eeprom_scl_in
add wave -noupdate /main/DUT/eeprom_scl_out
add wave -noupdate /main/DUT/vme_data_b_out
add wave -noupdate /main/DUT/vme_addr_b_out
add wave -noupdate /main/DUT/vme_lword_n_b_out
add wave -noupdate /main/DUT/vme_data_dir_int
add wave -noupdate /main/DUT/vme_addr_dir_int
add wave -noupdate /main/DUT/vme_ga
add wave -noupdate /main/DUT/vme_berr_n
add wave -noupdate /main/DUT/vme_irq_n
add wave -noupdate /main/DUT/vme_access_led
add wave -noupdate /main/DUT/sfp_sda_in
add wave -noupdate /main/DUT/sfp_sda_out
add wave -noupdate /main/DUT/sfp_scl_in
add wave -noupdate /main/DUT/sfp_scl_out
add wave -noupdate /main/DUT/pps
add wave -noupdate /main/DUT/pps_led
add wave -noupdate /main/DUT/pps_ext_in
add wave -noupdate /main/DUT/svec_led
add wave -noupdate /main/DUT/wr_led_link
add wave -noupdate /main/DUT/wr_led_act
add wave -noupdate /main/DUT/irq_vector
add wave -noupdate /main/DUT/ddr_axi4_out
add wave -noupdate /main/DUT/ddr_axi4_in
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {73840400 fs} 0}
configure wave -namecolwidth 252
configure wave -valuecolwidth 364
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits fs
update
WaveRestoreZoom {0 fs} {858329180 fs}
files = [
"svec7_test_top.vhd",
]
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