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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
9267db92
Commit
9267db92
authored
Jul 01, 2020
by
Tristan Gingold
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vmecore_test: add reload counter
parent
9bde4b57
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40 additions
and
6 deletions
+40
-6
vmecore_test.vhd
hdl/top/vmecore_test/vmecore_test.vhd
+40
-6
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hdl/top/vmecore_test/vmecore_test.vhd
View file @
9267db92
...
...
@@ -61,6 +61,8 @@ architecture rtl of vmecore_test is
-- 0x3000: pattern ram (0x1000 * 4B)
-- 0x4000 - 0x3ff000: pattern ram
signal
counter
:
unsigned
(
31
downto
0
);
signal
delay_counter
:
unsigned
(
31
downto
0
);
signal
reload_counter
:
unsigned
(
31
downto
0
);
signal
irq_status
:
std_logic
;
signal
leds
:
std_logic_vector
(
15
downto
0
);
...
...
@@ -101,6 +103,21 @@ begin
end
if
;
end
pattern_write
;
function
write_reg
(
val
:
unsigned
(
31
downto
0
);
sel
:
std_logic_vector
(
3
downto
0
);
dat
:
std_logic_vector
(
31
downto
0
))
return
unsigned
is
variable
res
:
unsigned
(
31
downto
0
);
begin
res
:
=
val
;
for
i
in
3
downto
0
loop
if
sel
(
i
)
=
'1'
then
res
(
8
*
i
+
7
downto
8
*
i
)
:
=
unsigned
(
dat
(
8
*
i
+
7
downto
8
*
i
));
end
if
;
end
loop
;
return
res
;
end
write_reg
;
variable
idx
:
natural
;
begin
if
rising_edge
(
clk_sys_i
)
then
...
...
@@ -109,6 +126,8 @@ begin
if
rst_n_i
=
'0'
then
counter
<=
(
others
=>
'0'
);
delay_counter
<=
(
others
=>
'0'
);
reload_counter
<=
(
others
=>
'0'
);
leds
<=
(
others
=>
'0'
);
nbr_read
<=
(
others
=>
'0'
);
nbr_write
<=
(
others
=>
'0'
);
...
...
@@ -123,6 +142,10 @@ begin
if
counter
=
1
then
int_o
<=
'1'
;
irq_status
<=
'1'
;
if
reload_counter
/=
0
then
counter
<=
delay_counter
;
reload_counter
<=
reload_counter
-
1
;
end
if
;
end
if
;
end
if
;
...
...
@@ -172,12 +195,16 @@ begin
when
"10"
=>
case
slave_i
.
adr
(
2
downto
0
)
is
when
"000"
=>
for
i
in
3
downto
0
loop
if
slave_i
.
sel
(
i
)
=
'1'
then
counter
(
8
*
i
+
7
downto
8
*
i
)
<=
unsigned
(
slave_i
.
dat
(
8
*
i
+
7
downto
8
*
i
));
end
if
;
end
loop
;
-- delay
counter
<=
write_reg
(
counter
,
slave_i
.
sel
,
slave_i
.
dat
);
when
"001"
=>
-- Interrupt status
when
"010"
=>
-- reload delay
delay_counter
<=
write_reg
(
delay_counter
,
slave_i
.
sel
,
slave_i
.
dat
);
when
"011"
=>
-- reload counter
reload_counter
<=
write_reg
(
reload_counter
,
slave_i
.
sel
,
slave_i
.
dat
);
when
others
=>
null
;
end
case
;
...
...
@@ -221,10 +248,17 @@ begin
when
"10"
=>
case
slave_i
.
adr
(
2
downto
0
)
is
when
"000"
=>
-- counter
slave_o
.
dat
<=
std_logic_vector
(
counter
);
when
"001"
=>
slave_o
.
dat
<=
(
0
=>
irq_status
,
others
=>
'0'
);
irq_status
<=
'0'
;
when
"010"
=>
-- delay
slave_o
.
dat
<=
std_logic_vector
(
delay_counter
);
when
"011"
=>
-- reload
slave_o
.
dat
<=
std_logic_vector
(
reload_counter
);
when
others
=>
slave_o
.
dat
<=
(
others
=>
'0'
);
end
case
;
...
...
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