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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
a4637f37
Commit
a4637f37
authored
May 20, 2020
by
Federico Vaga
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Merge branch 'release/v1.4.11' into develop
parents
3cd3234e
1b803764
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13 additions
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6 deletions
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-6
CHANGELOG.rst
CHANGELOG.rst
+9
-2
svec_base_wr.vhd
hdl/rtl/svec_base_wr.vhd
+4
-4
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CHANGELOG.rst
View file @
a4637f37
...
...
@@ -2,8 +2,14 @@
Change Log
==========
[1.4.11] 2020-05-20
===================
Added
-----
- [hdl] export DDMTD clock output
[1.4.10] 2020-05-12
==================
==================
=
Added
-----
- [hdl] metadata source-id automatic assignment
...
...
@@ -46,7 +52,8 @@ Fixed
-----
- [hdl] DDR constraints
- [hdl] DDR controller generic values are now properly capitalised
- [sw] Update svec-flasher to work with new type of flash memory used in newer SVEC boards
- [sw] Update svec-flasher to work with new type of flash memory used in
newer SVEC boards
[1.4.6] 2019-12-16
==================
...
...
hdl/rtl/svec_base_wr.vhd
View file @
a4637f37
...
...
@@ -365,7 +365,7 @@ architecture top of svec_base_wr is
signal
csr_ddr4_data_wack
:
std_logic
;
signal
csr_ddr4_data_rack
:
std_logic
;
--
--
signal
ddr4_read_ip
:
std_logic
;
signal
ddr4_write_ip
:
std_logic
;
...
...
@@ -404,7 +404,7 @@ architecture top of svec_base_wr is
signal
vme_ga
:
std_logic_vector
(
5
downto
0
);
signal
vme_berr_n
:
std_logic
;
signal
vme_irq_n
:
std_logic_vector
(
7
downto
1
);
-- The wishbone bus to the carrier part.
signal
carrier_wb_out
:
t_wishbone_slave_out
;
signal
carrier_wb_in
:
t_wishbone_slave_in
;
...
...
@@ -593,7 +593,7 @@ begin -- architecture top
csr_ddr4_addr_i
=>
csr_ddr4_addr
,
csr_ddr4_addr_o
=>
csr_ddr4_addr_out
,
csr_ddr4_addr_wr_o
=>
csr_ddr4_addr_wr
,
-- data to read or to write in ddr4
csr_ddr4_data_i
=>
csr_ddr4_data_in
,
csr_ddr4_data_o
=>
csr_ddr4_data_out
,
...
...
@@ -613,7 +613,7 @@ begin -- architecture top
csr_ddr5_data_rd_o
=>
csr_ddr5_data_rd
,
csr_ddr5_data_wack_i
=>
csr_ddr5_data_wack
,
csr_ddr5_data_rack_i
=>
csr_ddr5_data_rack
,
-- Thermometer and unique id
therm_id_i
=>
therm_id_in
,
therm_id_o
=>
therm_id_out
,
...
...
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