svec_base_wr: added DDMTD clock output

aecdf57f · Tomasz Wlostowski · 410df44d · aecdf57f
Commit aecdf57f authored Oct 15, 2019 by Tomasz Wlostowski
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Showing with 14 additions and 6 deletions

svec_base_wr.vhd hdl/rtl/svec_base_wr.vhd +14 -6

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--- a/hdl/rtl/svec_base_wr.vhd
+++ b/hdl/rtl/svec_base_wr.vhd
@@ -271,6 +271,9 @@ entity svec_base_wr is
    clk_ref_125m_o    : out std_logic;
    rst_ref_125m_n_o  : out std_logic;

+    -- 125 MHz DDMTD clock output
+    clk_dmtd_125m_o : out std_logic;
+
    --  Interrupts
    irq_user_i : in std_logic_vector(g_NUM_USER_IRQ + 5 downto 6) := (others => '0');

@@ -469,6 +472,8 @@ architecture top of svec_base_wr is
  signal sfp_scl_in  : std_logic;
  signal sfp_scl_out : std_logic;

+  signal clk_dmtd_125m : std_logic;
+
  attribute keep                 : string;
  attribute keep of clk_sys_62m5 : signal is "TRUE";
  attribute keep of clk_ref_125m : signal is "TRUE";
@@ -840,6 +845,7 @@ begin  -- architecture top
        clk_sys_62m5_o      => clk_sys_62m5,
        clk_ref_125m_o      => clk_ref_125m,
        clk_pll_aux_o       => clk_pll_aux,
+        clk_dmtd_125m_o     => clk_dmtd_125m,
        rst_sys_62m5_n_o    => rst_sys_62m5_n,
        rst_ref_125m_n_o    => rst_ref_125m_n,
        rst_pll_aux_n_o     => rst_pll_aux_n,
@@ -1433,4 +1439,6 @@ begin  -- architecture top
  ddr5_wb_o.err <= '0';
  ddr5_wb_o.rty <= '0';

+  clk_dmtd_125m_o <= clk_dmtd_125m;
+
 end architecture top;