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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
b2d7a10f
Commit
b2d7a10f
authored
Apr 02, 2014
by
Tomasz Wlostowski
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hdl/golden: updated manifest & ISE project
parent
1bf411bd
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2 changed files
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151 additions
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151 deletions
+151
-151
svec_top.xise
hdl/syn/golden/svec_top.xise
+150
-150
Manifest.py
hdl/top/golden/Manifest.py
+1
-1
No files found.
hdl/syn/golden/svec_top.xise
View file @
b2d7a10f
...
...
@@ -19,6 +19,9 @@
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
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xil_pn:type=
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"../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v"
xil_pn:type=
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/>
</autoManagedFiles>
<properties>
...
...
@@ -32,7 +35,7 @@
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...
...
@@ -129,7 +132,8 @@
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...
...
@@ -152,7 +156,7 @@
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...
...
@@ -214,7 +218,6 @@
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...
...
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</properties>
...
...
@@ -338,418 +341,415 @@
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<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
138
"
/>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"
5
"
/>
</file>
</files>
...
...
hdl/top/golden/Manifest.py
View file @
b2d7a10f
files
=
[
"svec_top.vhd"
,
"svec_top.ucf"
,
"
xvme64x_core.vhd"
,
"
synthesis_descriptor.vhd"
]
files
=
[
"svec_top.vhd"
,
"svec_top.ucf"
,
"synthesis_descriptor.vhd"
]
fetchto
=
"../../ip_cores"
...
...
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