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S
Simple VME FMC Carrier SVEC
Commit d1acc791 authored by Federico Vaga's avatar Federico Vaga
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*.o
*.ko
*.mod.c
.*.o.cmd
.*.ko.cmd
*.mod.d
*.o.d
*.tmp
.tmp_versions
modules.order
Module.symvers
\#*
*~
CHANGELOG 0 → 100644
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# Change Log
## [0.9.0] - 2017-10-13
### Added
- unittest
### Fixes
- add missing header in the repository
- add delay in the unlocking sequence
## [0.8.0] - 2017-10-12
### Added
- char device to program the Application FPGA
- sysfs attribute to unlock programming
- documentation!
## [0.0.0] - 2017-09-28
### Added
- basic Linux device driver
\ No newline at end of file
LICENSE 0 → 100644
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Makefile 0 → 100644
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-include Makefile.specific
# include parent_common.mk for buildsystem's defines
#use absolute path for REPO_PARENT
REPO_PARENT ?= $(shell /bin/pwd)/..
-include $(REPO_PARENT)/parent_common.mk
DIRS = kernel doc
.PHONY: all clean modules install modules_install $(DIRS)
all clean modules install modules_install: $(DIRS)
clean: TARGET = clean
modules: TARGET = modules
install: TARGET = install
modules_install: TARGET = modules_install
$(DIRS):
$(MAKE) -C $@ $(TARGET)
README.rst 0 → 100644
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.. image:: ./doc/svec-logo.png
SVEC Driver
===========
This is the simplified version of the SVEC driver which only purpose is
to export an interface to enable the users to program their bitstream on
the SVEC FPGA.
Build Sources
=============
In order to be able to build this SVEC driver you need the VMEBUS sources
at hand, otherwise you cannot compile the kernel sources.
The documentation is written in reStructuredText and it generates HTML files
and man pages. For this you need the python docutils package installed
If the requirements are satified you can run the following commant in
the project root directory:
.. code::
make VMEBUS=/path/to/vmebus/
Futuristic Vision
=================
Actually this is not a driver for the SVEC card but for that little gateware
core in the SVEC bootloader FPGA. In the future we can think about standardize
other designs around this concept. Then this driver will become the FPGA
programmer driver for a set of devices.
doc/.gitignore 0 → 100644
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*.man
*.html
*.pdf
\ No newline at end of file
doc/Makefile 0 → 100644
View file @ d1acc791
MANUAL=svec-device
all: img doc
doc: html man
html:
rst2html $(MANUAL).rst > $(MANUAL).html
man:
rst2man --syntax-highlight=none $(MANUAL).rst > $(MANUAL).man
img: svec-logo.png
svec-logo.png: svec-logo.svg
inkscape -f $< -e $@
clean:
rm -f *.html *.man *.png
doc/svec-device.rst 0 → 100644
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====
SVEC
====
---------------------------------------------
programming application FPGA
---------------------------------------------
:Author: Federico Vaga <federico.vaga@cern.ch>
:organization: CERN
:Date: 2017-10-12
:Copyright: GNU GPL, version 2 or any later version
:Version: 0.9.0
:Manual section: 4
:Manual group: CERN BECOHT Toolkit
Description
===========
The file ``/dev/svec.[0-N]`` is a character device, usually of mode 0440
and owner root:root. The number ``[0-N]`` represents a *SVEC Module* instance.
It is used to program the *Application FPGA* of a `SVEC module`_ on the VME bus.
The programming procedure consists in taking an FPGA bit-stream from the user
and writing it in the Application FPGA on the SVEC Module.
Once the device has been closed the Application FPGA become active and,
if valid, it will run the FPGA bit-stream provided by the user.
In order to prevent accidental programming, the Application FPGA programming
procedure is protected by the sysfs attribute ``AFPGA/lock``, usually of mode
0644 and owner root:root. On read it returns a string representing the current
locking status. On write it accepts only the strings:
- "unlock" to unlock the programming procedure.
- "lock" to lock the programming procedure
Once the programming procedure has been completed, the device go back to the
locking status.
The complete programming procedure is:
#. unlock the programming procedure by writing "unlock" in ``AFPGA/lock``
#. write the FPGA bit-stream in the character device ``/dev/svec.<N>``
Files
=====
/dev/svec.[0-N]
/sys/bus/vme/device/vme.[0-N]/svec/svec.[0-N]/AFPGA/lock
.. _`SVEC module`: https://www.ohwr.org/projects/svec/
Examples
========
.. code:: sh
echo "unlock" > /sys/bus/vme/devices/vme.8/svec/svec.8/AFPGA/lock
dd if=/path/to/bitstream.bin of=/dev/svec.8
.. code:: sh
echo "unlock" > /sys/bus/vme/devices/vme.8/svec/svec.8/AFPGA/lock
cat /path/to/bitstream.bin > /dev/svec.8
doc/svec-logo.svg 0 → 100644
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kernel/Kbuild 0 → 100644
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# add versions of supermodule. It is useful when svec-sw is included as sub-module
# of a bigger project that we want to track
ifdef CONFIG_SUPER_REPO
ifdef CONFIG_SUPER_REPO_VERSION
SUBMODULE_VERSIONS += MODULE_INFO(version_$(CONFIG_SUPER_REPO),\"$(CONFIG_SUPER_REPO_VERSION)\");
endif
endif
# add versions of used submodules
ccflags-y += -DADDITIONAL_VERSIONS="$(SUBMODULE_VERSIONS)"
ccflags-y += -DGIT_VERSION=\"$(GIT_VERSION)\"
ccflags-y += -I$(VMEBRIDGE_ABS)/include -I$(FPGA_MGR_ABS)/include
KBUILD_EXTRA_SYMBOLS += $(VMEBRIDGE_ABS)/driver/Module.symvers
KBUILD_EXTRA_SYMBOLS += $(FPGA_MGR_ABS)/drivers/fpga/Module.symvers
obj-m := svec.o
svec-objs := svec-core.o
kernel/Makefile 0 → 100644
View file @ d1acc791
# include parent_common.mk for buildsystem's defines
#use absolute path for REPO_PARENT
REPO_PARENT ?= $(shell /bin/pwd)/../..
-include $(REPO_PARENT)/parent_common.mk
LINUX ?= /lib/modules/$(shell uname -r)/build
VMEBRIDGE_ABS ?= $(abspath $(VMEBRIDGE))
FPGA_MGR_ABS ?= $(abspath $(FPGA_MGR))
GIT_VERSION = $(shell git describe --dirty --long --tags)
export GIT_VERSION
all: modules
.PHONY: all modules clean help install modules_install
modules help install modules_install:
$(MAKE) -C $(LINUX) M=$(shell pwd) GIT_VERSION=$(GIT_VERSION) VMEBRIDGE_ABS=$(VMEBRIDGE_ABS) FPGA_MGR_ABS=$(FPGA_MGR_ABS) $@
# be able to run the "clean" rule even if $(LINUX) is not valid
clean:
rm -rf *.o *~ .*.cmd *.ko *.mod.c .tmp_versions Module.symvers \
Module.markers modules.order
kernel/hw/xloader_regs.h 0 → 100644
View file @ d1acc791
/*
Register definitions for slave core: Xilinx FPGA loader
* File : xloader_regs.h
* Author : auto-generated by wbgen2 from xloader_wb.wb
* Created : Thu Jun 21 15:17:30 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xloader_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_XLOADER_WB_WB
#define __WBGEN2_REGDEFS_XLOADER_WB_WB
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control/status register */
/* definitions for field: Start configuration in reg: Control/status register */
#define XLDR_CSR_START WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Configuration done in reg: Control/status register */
#define XLDR_CSR_DONE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Configuration error in reg: Control/status register */
#define XLDR_CSR_ERROR WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Loader busy in reg: Control/status register */
#define XLDR_CSR_BUSY WBGEN2_GEN_MASK(3, 1)
/* definitions for field: Byte order select in reg: Control/status register */
#define XLDR_CSR_MSBF WBGEN2_GEN_MASK(4, 1)
/* definitions for field: Software resest in reg: Control/status register */
#define XLDR_CSR_SWRST WBGEN2_GEN_MASK(5, 1)
/* definitions for field: Exit bootloader mode in reg: Control/status register */
#define XLDR_CSR_EXIT WBGEN2_GEN_MASK(6, 1)
/* definitions for field: Serial clock divider in reg: Control/status register */
#define XLDR_CSR_CLKDIV_MASK WBGEN2_GEN_MASK(8, 6)
#define XLDR_CSR_CLKDIV_SHIFT 8
#define XLDR_CSR_CLKDIV_W(value) WBGEN2_GEN_WRITE(value, 8, 6)
#define XLDR_CSR_CLKDIV_R(reg) WBGEN2_GEN_READ(reg, 8, 6)
/* definitions for register: Bootloader Trigger Register */
/* definitions for register: GPIO Output Register */
/* definitions for register: ID Register */
/* definitions for register: FIFO 'Bitstream FIFO' data input register 0 */
/* definitions for field: Entry size in reg: FIFO 'Bitstream FIFO' data input register 0 */
#define XLDR_FIFO_R0_XSIZE_MASK WBGEN2_GEN_MASK(0, 2)
#define XLDR_FIFO_R0_XSIZE_SHIFT 0
#define XLDR_FIFO_R0_XSIZE_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
#define XLDR_FIFO_R0_XSIZE_R(reg) WBGEN2_GEN_READ(reg, 0, 2)
/* definitions for field: Last xfer in reg: FIFO 'Bitstream FIFO' data input register 0 */
#define XLDR_FIFO_R0_XLAST WBGEN2_GEN_MASK(2, 1)
/* definitions for register: FIFO 'Bitstream FIFO' data input register 1 */
/* definitions for field: Data in reg: FIFO 'Bitstream FIFO' data input register 1 */
#define XLDR_FIFO_R1_XDATA_MASK WBGEN2_GEN_MASK(0, 32)
#define XLDR_FIFO_R1_XDATA_SHIFT 0
#define XLDR_FIFO_R1_XDATA_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define XLDR_FIFO_R1_XDATA_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'Bitstream FIFO' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'Bitstream FIFO' control/status register */
#define XLDR_FIFO_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'Bitstream FIFO' control/status register */
#define XLDR_FIFO_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO clear in reg: FIFO 'Bitstream FIFO' control/status register */
#define XLDR_FIFO_CSR_CLEAR_BUS WBGEN2_GEN_MASK(18, 1)
/* definitions for field: FIFO counter in reg: FIFO 'Bitstream FIFO' control/status register */
#define XLDR_FIFO_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define XLDR_FIFO_CSR_USEDW_SHIFT 0
#define XLDR_FIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define XLDR_FIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* [0x0]: REG Control/status register */
#define XLDR_REG_CSR 0x00000000
/* [0x4]: REG Bootloader Trigger Register */
#define XLDR_REG_BTRIGR 0x00000004
/* [0x8]: REG GPIO Output Register */
#define XLDR_REG_GPIOR 0x00000008
/* [0xc]: REG ID Register */
#define XLDR_REG_IDR 0x0000000c
/* [0x10]: REG FIFO 'Bitstream FIFO' data input register 0 */
#define XLDR_REG_FIFO_R0 0x00000010
/* [0x14]: REG FIFO 'Bitstream FIFO' data input register 1 */
#define XLDR_REG_FIFO_R1 0x00000014
/* [0x18]: REG FIFO 'Bitstream FIFO' control/status register */
#define XLDR_REG_FIFO_CSR 0x00000018
#endif
kernel/svec-core.c 0 → 100644
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This diff is collapsed.
unittest/SvecTestProgramming.py 0 → 100644
View file @ d1acc791
import os
import unittest
class SvecTestProgramming(unittest.TestCase):
def setUp(self):
slot = os.environ["VME_SLOT"]
self.file_path = "/sys/bus/vme/devices/vme.{}/svec/svec.{}/AFPGA/lock".format(slot, slot)
self.dev_path = "/dev/svec.{}".format(slot)
self.bitstream = os.environ["BITSTREAM"]
def test_01(self):
"""It writes a dummy FPGA bitstream"""
with open(self.file_path, "w") as f:
f.write("unlock")
with open(self.bitstream, "rb") as d:
with open(self.dev_path, "wb") as f:
f.write(d.read())
with open(self.file_path, "r") as f:
val = f.read().strip()
self.assertEqual(val, "locked")
unittest/SvecTestProgrammingLock.py 0 → 100644
View file @ d1acc791
import os
import random
import string
import unittest
class SvecTestProgrammingLock(unittest.TestCase):
def setUp(self):
slot = os.environ["VME_SLOT"]
self.file_path = "/sys/bus/vme/devices/vme.{}/svec/svec.{}/AFPGA/lock".format(slot, slot)
self.dev_path = "/dev/svec.{}".format(slot)
def test_01(self):
"""It flips the previous lock status"""
with open(self.file_path, "r") as f:
val = f.read().strip()
for i in range(2):
new = "lock" if val == "unlocked" else "unlock"
with open(self.file_path, "w") as f:
f.write(new)
with open(self.file_path, "r") as f:
val = f.read().strip()
self.assertEqual(val, "{}ed".format(new))
def test_02(self):
"""It writes invalid commands to the lock attribute"""
chars = (random.choice(string.ascii_uppercase) for _ in range(3))
with self.assertRaises(OSError):
with open(self.file_path) as f:
f.write(''.join(chars))
def test_03(self):
"""It unlocks the programming"""
with open(self.file_path, "w") as f:
f.write("unlock")
with open(self.file_path, "r") as f:
val = f.read().strip()
self.assertEqual(val, "unlocked")
# we should be able to open the device
with open(self.dev_path) as f:
pass
# It should lock automatically
with open(self.file_path, "r") as f:
val = f.read().strip()
self.assertEqual(val, "locked")
def test_04(self):
"""It locks the programming"""
with open(self.file_path, "w") as f:
f.write("lock")
with open(self.file_path, "r") as f:
val = f.read().strip()
self.assertEqual(val, "locked")
# we should not be able to open the device
with self.assertRaises(OSError):
f = open(self.dev_path)
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