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Simple VME FMC Carrier SVEC
Commit d2d407bd authored by Tristan Gingold's avatar Tristan Gingold
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Add vmespy application.

parent 7c99d176
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hdl/syn/vmespy/Manifest.py 0 → 100644
View file @ d2d407bd
target = "xilinx"
action = "synthesis"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg900"
syn_top = "svec_vmespy_top"
syn_project = "svec_vmespy_top.xise"
syn_tool = "ise"
modules = {
"local" : [
"../../top/vmespy",
],
}
hdl/top/vmespy/Manifest.py 0 → 100644
View file @ d2d407bd
files = [
"svec_vmespy_top.vhd",
"svec_vmespy_top.ucf",
"vmespy.vhd",
]
modules = { "git": [ "git://ohwr.org/project/general-cores.git",
"git://ohwr.org/project/vme64x-core.git" ]
}
hdl/top/vmespy/svec_vmespy_top.ucf 0 → 100644
View file @ d2d407bd
#===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = R1;
NET "vme_sysreset_n_i" LOC = P4;
NET "vme_retry_oe_o" LOC = R4;
NET "vme_retry_n_o" LOC = AB2;
NET "vme_lword_n_b" LOC = M7;
NET "vme_iackout_n_o" LOC = N3;
NET "vme_iackin_n_i" LOC = P7;
NET "vme_iack_n_i" LOC = N1;
NET "vme_dtack_oe_o" LOC = T1;
NET "vme_dtack_n_o" LOC = R5;
NET "vme_ds_n_i[1]" LOC = Y6;
NET "vme_ds_n_i[0]" LOC = Y7;
NET "vme_data_oe_n_o" LOC = P1;
NET "vme_data_dir_o" LOC = P2;
NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_o[7]" LOC = R7;
NET "vme_irq_o[6]" LOC = AH2;
NET "vme_irq_o[5]" LOC = AF2;
NET "vme_irq_o[4]" LOC = N9;
NET "vme_irq_o[3]" LOC = N10;
NET "vme_irq_o[2]" LOC = AH4;
NET "vme_irq_o[1]" LOC = AG4;
NET "vme_gap_i" LOC = M6;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
NET "vme_ga_i[2]" LOC = AJ1;
NET "vme_ga_i[1]" LOC = AH1;
NET "vme_ga_i[0]" LOC = V7;
NET "vme_data_b[31]" LOC = AK3;
NET "vme_data_b[30]" LOC = AH3;
NET "vme_data_b[29]" LOC = T8;
NET "vme_data_b[28]" LOC = T9;
NET "vme_data_b[27]" LOC = AK4;
NET "vme_data_b[26]" LOC = AJ4;
NET "vme_data_b[25]" LOC = W6;
NET "vme_data_b[24]" LOC = W7;
NET "vme_data_b[23]" LOC = AB6;
NET "vme_data_b[22]" LOC = AB7;
NET "vme_data_b[21]" LOC = W9;
NET "vme_data_b[20]" LOC = W10;
NET "vme_data_b[19]" LOC = AK5;
NET "vme_data_b[18]" LOC = AH5;
NET "vme_data_b[17]" LOC = AD6;
NET "vme_data_b[16]" LOC = AC6;
NET "vme_data_b[15]" LOC = AA6;
NET "vme_data_b[14]" LOC = AA7;
NET "vme_data_b[13]" LOC = T6;
NET "vme_data_b[12]" LOC = T7;
NET "vme_data_b[11]" LOC = AG5;
NET "vme_data_b[10]" LOC = AE5;
NET "vme_data_b[9]" LOC = Y11;
NET "vme_data_b[8]" LOC = W11;
NET "vme_data_b[7]" LOC = AF6;
NET "vme_data_b[6]" LOC = AE6;
NET "vme_data_b[5]" LOC = Y8;
NET "vme_data_b[4]" LOC = Y9;
NET "vme_data_b[3]" LOC = AE7;
NET "vme_data_b[2]" LOC = AD7;
NET "vme_data_b[1]" LOC = AA9;
NET "vme_data_b[0]" LOC = AA10;
NET "vme_am_i[5]" LOC = V8;
NET "vme_am_i[4]" LOC = AG3;
NET "vme_am_i[3]" LOC = AF3;
NET "vme_am_i[2]" LOC = AF4;
NET "vme_am_i[1]" LOC = AE4;
NET "vme_am_i[0]" LOC = AK2;
NET "vme_addr_b[31]" LOC = T2;
NET "vme_addr_b[30]" LOC = T3;
NET "vme_addr_b[29]" LOC = T4;
NET "vme_addr_b[28]" LOC = U1;
NET "vme_addr_b[27]" LOC = U3;
NET "vme_addr_b[26]" LOC = U4;
NET "vme_addr_b[25]" LOC = U5;
NET "vme_addr_b[24]" LOC = V1;
NET "vme_addr_b[23]" LOC = V2;
NET "vme_addr_b[22]" LOC = W1;
NET "vme_addr_b[21]" LOC = W3;
NET "vme_addr_b[20]" LOC = AA4;
NET "vme_addr_b[19]" LOC = AA5;
NET "vme_addr_b[18]" LOC = Y1;
NET "vme_addr_b[17]" LOC = Y2;
NET "vme_addr_b[16]" LOC = Y3;
NET "vme_addr_b[15]" LOC = Y4;
NET "vme_addr_b[14]" LOC = AC1;
NET "vme_addr_b[13]" LOC = AC3;
NET "vme_addr_b[12]" LOC = AD1;
NET "vme_addr_b[11]" LOC = AD2;
NET "vme_addr_b[10]" LOC = AB3;
NET "vme_addr_b[9]" LOC = AB4;
NET "vme_addr_b[8]" LOC = AD3;
NET "vme_addr_b[7]" LOC = AD4;
NET "vme_addr_b[6]" LOC = AC4;
NET "vme_addr_b[5]" LOC = AC5;
NET "vme_addr_b[4]" LOC = N7;
NET "vme_addr_b[3]" LOC = N8;
NET "vme_addr_b[2]" LOC = AE1;
NET "vme_addr_b[1]" LOC = AE3;
NET "vme_write_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_sysreset_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD = "LVCMOS33";
NET "vme_iackout_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_iackin_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_iack_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD = "LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ds_n_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[7]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_gap_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[1]" IOSTANDARD = "LVCMOS33";
NET "vme_data_b[0]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[5]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[3]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[2]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[1]" IOSTANDARD = "LVCMOS33";
NET "vme_am_i[0]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[31]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[30]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[29]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[28]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[27]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[26]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[25]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[24]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[23]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[22]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[21]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[20]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[19]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[18]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[17]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[16]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[15]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[14]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[13]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[12]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[11]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[10]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[9]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[8]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[7]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[6]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[5]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[4]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[3]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[2]" IOSTANDARD = "LVCMOS33";
NET "vme_addr_b[1]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "rst_n_i" LOC = AD28;
NET "rst_n_i" IOSTANDARD = "LVCMOS33";
NET "clk_20m_vcxo_i" LOC = V26;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS33";
#NET "clk_125m_pllref_n_i" LOC = AB30;
#NET "clk_125m_pllref_p_i" LOC = AB28;
#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_gtp_p_i" LOC = B19;
#NET "clk_125m_gtp_n_i" LOC = A19;
#----------------------------------------
# SFP slot
#----------------------------------------
#NET "sfp_txp_o" LOC = B23;
#NET "sfp_txn_o" LOC = A23;
#NET "sfp_rxp_i" LOC = D22;
#NET "sfp_rxn_i" LOC = C22;
#NET "sfp_los_i" LOC = W25;
#NET "sfp_mod_def0_i" LOC = Y26;
#NET "sfp_mod_def1_b" LOC = Y27;
#NET "sfp_mod_def2_b" LOC = AA24;
#NET "sfp_rate_select_o" LOC = W24;
#NET "sfp_tx_disable_o" LOC = AA25;
#NET "sfp_tx_fault_i" LOC = AA27;
#NET "sfp_los_i" IOSTANDARD = "LVCMOS33";
#NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS33";
#NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS33";
#NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS33";
#NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS33";
#NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS33";
#NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Clock controls
#----------------------------------------
#NET "pll20dac_din_o" LOC = U28;
#NET "pll20dac_sclk_o" LOC = AA28;
#NET "pll20dac_sync_n_o" LOC = N28;
#NET "pll25dac_din_o" LOC = P25;
#NET "pll25dac_sclk_o" LOC = N27;
#NET "pll25dac_sync_n_o" LOC = P26;
#NET "pll20dac_din_o" IOSTANDARD = "LVCMOS33";
#NET "pll20dac_sclk_o" IOSTANDARD = "LVCMOS33";
#NET "pll20dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#NET "pll25dac_din_o" IOSTANDARD = "LVCMOS33";
#NET "pll25dac_sclk_o" IOSTANDARD = "LVCMOS33";
#NET "pll25dac_sync_n_o" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# SPI FLASH
#----------------------------------------
#NET "spi_ncs_o" LOC = AG27;
#NET "spi_ncs_o" IOSTANDARD = "LVCMOS33";
#NET "spi_sclk_o" LOC = AG26;
#NET "spi_sclk_o" IOSTANDARD = "LVCMOS33";
#NET "spi_mosi_o" LOC = AH26;
#NET "spi_mosi_o" IOSTANDARD = "LVCMOS33";
#NET "spi_miso_i" LOC = AH27;
#NET "spi_miso_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# UART
#----------------------------------------
#NET "uart_txd_o" LOC = U27;
#NET "uart_rxd_i" LOC = U25;
#NET "uart_txd_o" IOSTANDARD = "LVCMOS33";
#NET "uart_rxd_i" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# 1-wire thermoeter + unique ID
#----------------------------------------
#NET "onewire_b" LOC = AC30;
#NET "onewire_b" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Front panel LEDs
#----------------------------------------
NET "fp_led_line_oen_o[0]" LOC = AD26;
NET "fp_led_line_oen_o[1]" LOC = AD27;
NET "fp_led_line_o[0]" LOC = AC27;
NET "fp_led_line_o[1]" LOC = AC28;
NET "fp_led_column_o[0]" LOC = AE30;
NET "fp_led_column_o[1]" LOC = AE27;
NET "fp_led_column_o[2]" LOC = AE28;
NET "fp_led_column_o[3]" LOC = AF28;
NET "fp_led_line_oen_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_oen_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_line_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[0]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[1]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[2]" IOSTANDARD="LVCMOS33";
NET "fp_led_column_o[3]" IOSTANDARD="LVCMOS33";
#----------------------------------------
# Front panel IOs
#----------------------------------------
#NET "fp_gpio1_o" LOC = T28;
#NET "fp_gpio2_o" LOC = R30;
#NET "fp_gpio3_i" LOC = V27;
#NET "fp_gpio4_i" LOC = U29;
#NET "fp_gpio1_a2b_o" LOC = T30;
#NET "fp_gpio2_a2b_o" LOC = R29;
#NET "fp_gpio34_a2b_o" LOC = V28;
#NET "fp_term_en_o[1]" LOC = AB1;
#NET "fp_term_en_o[2]" LOC = W5;
#NET "fp_term_en_o[3]" LOC = W4;
#NET "fp_term_en_o[4]" LOC = V4;
#NET "fp_gpio1_o" IOSTANDARD = "LVCMOS33";
#NET "fp_gpio2_o" IOSTANDARD = "LVCMOS33";
#NET "fp_gpio3_i" IOSTANDARD = "LVCMOS33";
#NET "fp_gpio4_i" IOSTANDARD = "LVCMOS33";
#NET "fp_gpio1_a2b_o" IOSTANDARD = "LVCMOS33";
#NET "fp_gpio2_a2b_o" IOSTANDARD = "LVCMOS33";
#NET "fp_gpio34_a2b_o" IOSTANDARD = "LVCMOS33";
#NET "fp_term_en_o[1]" IOSTANDARD = "LVCMOS33";
#NET "fp_term_en_o[2]" IOSTANDARD = "LVCMOS33";
#NET "fp_term_en_o[3]" IOSTANDARD = "LVCMOS33";
#NET "fp_term_en_o[4]" IOSTANDARD = "LVCMOS33";
#----------------------------------------
# Carrier I2C EEPROM
#----------------------------------------
#NET "carrier_scl_b" LOC = AC29;
#NET "carrier_sda_b" LOC = AA30;
#NET "carrier_scl_b" IOSTANDARD = "LVCMOS33";
#NET "carrier_sda_b" IOSTANDARD = "LVCMOS33";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
#NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
#TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
#NET "clk_125m_gtp_n_i" TNM_NET = clk_125m_gtp_n_i;
#TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo_i";
TIMESPEC TS_clk_20m_vcxo_i = PERIOD "clk_20m_vcxo_i" 50 ns HIGH 50%;
# external 10MHz clock input
#NET "fp_gpio3_i" TNM_NET = fp_gpio3_i;
#TIMESPEC TS_fp_gpio3_i = PERIOD "fp_gpio3_i" 100 ns HIGH 50%;
#NET "clk_ref_125m" TNM_NET = clk_ref_125m;
#NET "clk_sys_62m5" TNM_NET = clk_sys_62m5;
#TIMESPEC TS_crossdomain_01 = FROM "clk_ref_125m" TO "clk_sys_62m5" 4ns DATAPATHONLY;
#TIMESPEC TS_crossdomain_02 = FROM "clk_sys_62m5" TO "clk_ref_125m" 4ns DATAPATHONLY;
# External async resets
NET "rst_n_i" TIG;
NET "vme_sysreset_n_i" TIG;
# Force PPS output to always be placed as IOB register
#INST "cmp_xwrc_board_svec/cmp_board_common/cmp_xwr_core/wrpc/pps_gen/wrapped_ppsgen/pps_out_o" IOB = FORCE;
INST "vme_irq_o[7]" IOB=FORCE;
INST "vme_irq_o[6]" IOB=FORCE;
INST "vme_irq_o[5]" IOB=FORCE;
INST "vme_irq_o[4]" IOB=FORCE;
INST "vme_irq_o[3]" IOB=FORCE;
INST "vme_irq_o[2]" IOB=FORCE;
INST "vme_irq_o[1]" IOB=FORCE;
hdl/top/vmespy/svec_vmespy_top.vhd 0 → 100644
View file @ d2d407bd
-------------------------------------------------------------------------------
-- Title : VME64xCore test design for SVEC
-- Project : VME64xCore
-- URL : https://www.ohwr.org/projects/vme64x-core
-------------------------------------------------------------------------------
-- File : svec_vmecore_test.vhd
-- Author(s) : Tristan Gingold <tristan.gingold@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-09-19
-- Last update: 2020-01-16
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the test design .
--
-------------------------------------------------------------------------------
-- Copyright (c) 2017 CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.vme64x_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity svec_vmespy_top is
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset from system fpga
rst_n_i : in std_logic;
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
---------------------------------------------------------------------------
-- VME interface
---------------------------------------------------------------------------
vme_write_n_i : in std_logic;
vme_sysreset_n_i : in std_logic;
vme_retry_oe_o : out std_logic;
vme_retry_n_o : out std_logic;
vme_lword_n_b : inout std_logic;
vme_iackout_n_o : out std_logic;
vme_iackin_n_i : in std_logic;
vme_iack_n_i : in std_logic;
vme_gap_i : in std_logic;
vme_dtack_oe_o : out std_logic;
vme_dtack_n_o : out std_logic;
vme_ds_n_i : in std_logic_vector(1 downto 0);
vme_data_oe_n_o : out std_logic;
vme_data_dir_o : out std_logic;
vme_berr_o : out std_logic;
vme_as_n_i : in std_logic;
vme_addr_oe_n_o : out std_logic;
vme_addr_dir_o : out std_logic;
vme_irq_o : out std_logic_vector(7 downto 1);
vme_ga_i : in std_logic_vector(4 downto 0);
vme_data_b : inout std_logic_vector(31 downto 0);
vme_am_i : in std_logic_vector(5 downto 0);
vme_addr_b : inout std_logic_vector(31 downto 1);
---------------------------------------------------------------------------
-- Carrier front panel LEDs and IOs
---------------------------------------------------------------------------
fp_led_line_oen_o : out std_logic_vector(1 downto 0);
fp_led_line_o : out std_logic_vector(1 downto 0);
fp_led_column_o : out std_logic_vector(3 downto 0)
);
end entity svec_vmespy_top;
architecture top of svec_vmespy_top is
-- Wishbone bus from master
signal master_out : t_wishbone_master_out;
signal master_in : t_wishbone_master_in;
-- VME
signal vme_data_b_out : std_logic_vector(31 downto 0);
signal vme_addr_b_out : std_logic_vector(31 downto 1);
signal vme_lword_n_b_out : std_logic;
signal vme_data_dir_int : std_logic;
signal vme_addr_dir_int : std_logic;
signal vme_ga : std_logic_vector(5 downto 0);
signal vme_berr_n_o : std_logic;
signal vme_irq_n_o : std_logic_vector(7 downto 1);
signal vme_dtack_n : std_logic;
-- LEDs and GPIO
signal svec_led : std_logic_vector(15 downto 0);
signal pllout_clk_fb_sys, pllout_clk_sys : std_logic;
signal clk_20m_vcxo_buf : std_logic;
signal clk_sys : std_logic;
signal local_reset_n : std_logic;
signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
signal powerup_rst_n : std_logic := '0';
signal sys_locked : std_logic;
begin -- architecture top
p_powerup_reset : process(clk_sys)
begin
if rising_edge(clk_sys) then
if(vme_sysreset_n_i = '0' or rst_n_i = '0') then
powerup_rst_n <= '0';
elsif sys_locked = '1' then
if(powerup_reset_cnt = "11111111") then
powerup_rst_n <= '1';
else
powerup_rst_n <= '0';
powerup_reset_cnt <= powerup_reset_cnt + 1;
end if;
else
powerup_rst_n <= '0';
powerup_reset_cnt <= "00000000";
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- Clock distribution/PLL and reset
-------------------------------------------------------------------------------
-- Input is 20Mhz
U_cmp_sys_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50, -- 1Ghz
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8, -- 2*62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 2*62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_sys,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open, -- pllout_clk_sys,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => sys_locked,
RST => '0',
CLKFBIN => pllout_clk_fb_sys,
CLKIN => clk_20m_vcxo_buf);
U_Sync_Reset : gc_sync_ffs
port map (
clk_i => clk_sys,
rst_n_i => '1',
data_i => powerup_rst_n,
synced_o => local_reset_n);
U_cmp_clk_vcxo_buf : BUFG
port map (
O => clk_20m_vcxo_buf,
I => clk_20m_vcxo_i);
U_cmp_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
-----------------------------------------------------------------------------
-- VME64x Core and buffers
-----------------------------------------------------------------------------
-- BERR and IRQ vme signals are inverted by the drivers. See schematics.
vme_berr_o <= not vme_berr_n_o;
vme_irq_o <= not vme_irq_n_o;
vme_dtack_n_o <= vme_dtack_n;
inst_vme_core : xvme64x_core
generic map (
g_CLOCK_PERIOD => 8,
g_DECODE_AM => True,
g_USER_CSR_EXT => False,
g_wb_granularity => BYTE,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
vme_i.as_n => vme_as_n_i,
vme_i.rst_n => vme_sysreset_n_i,
vme_i.write_n => vme_write_n_i,
vme_i.am => vme_am_i,
vme_i.ds_n => vme_ds_n_i,
vme_i.ga => vme_ga,
vme_i.lword_n => vme_lword_n_b,
vme_i.addr => vme_addr_b,
vme_i.data => vme_data_b,
vme_i.iack_n => vme_iack_n_i,
vme_i.iackin_n => vme_iackin_n_i,
vme_o.berr_n => vme_berr_n_o,
vme_o.dtack_n => vme_dtack_n,
vme_o.retry_n => vme_retry_n_o,
vme_o.retry_oe => vme_retry_oe_o,
vme_o.lword_n => vme_lword_n_b_out,
vme_o.data => vme_data_b_out,
vme_o.addr => vme_addr_b_out,
vme_o.irq_n => vme_irq_n_o,
vme_o.iackout_n => vme_iackout_n_o,
vme_o.dtack_oe => vme_dtack_oe_o,
vme_o.data_dir => vme_data_dir_int,
vme_o.data_oe_n => vme_data_oe_n_o,
vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_i => master_in,
wb_o => master_out);
vme_ga <= vme_gap_i & vme_ga_i;
-- VME tri-state buffers
vme_data_b <= vme_data_b_out when vme_data_dir_int = '1'
else (others => 'Z');
vme_addr_b <= vme_addr_b_out when vme_addr_dir_int = '1'
else (others => 'Z');
vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1'
else 'Z';
vme_addr_dir_o <= vme_addr_dir_int;
vme_data_dir_o <= vme_data_dir_int;
-- tri-state Carrier EEPROM
-- carrier_sda_b <= 'Z';
-- carrier_scl_b <= 'Z';
-- Tristates for SFP EEPROM
-- sfp_mod_def1_b <= 'Z';
-- sfp_mod_def2_b <= 'Z';
-- tri-state onewire access
-- onewire_b <= 'Z';
------------------------------------------------------------------------------
-- Carrier front panel LEDs and LEMOs
------------------------------------------------------------------------------
cmp_led_controller : gc_bicolor_led_ctrl
generic map(
g_nb_column => 4,
g_nb_line => 2,
g_clk_freq => 62_500_000, -- in Hz
g_refresh_rate => 250 -- in Hz
)
port map(
rst_n_i => local_reset_n,
clk_i => clk_sys,
led_intensity_i => "1100100", -- in %
led_state_i => svec_led,
column_o => fp_led_column_o,
line_o => fp_led_line_o,
line_oen_o => fp_led_line_oen_o);
inst_test: entity work.vmespy
port map (clk_sys_i => clk_sys,
rst_n_i => local_reset_n,
slave_i => master_out,
slave_o => master_in,
leds_o => svec_led,
vme_write_n_i => vme_write_n_i,
vme_lword_n_i => vme_lword_n_b,
vme_iack_n_i => vme_iack_n_i,
vme_dtack_n_i => vme_dtack_n,
vme_ds_n_i => vme_ds_n_i,
vme_as_n_i => vme_as_n_i,
vme_data_i => vme_data_b,
vme_am_i => vme_am_i,
vme_addr_i => vme_addr_b);
end architecture top;
hdl/top/vmespy/vmespy.vhd 0 → 100644
View file @ d2d407bd
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- WB slave test bench for vme64x core
-- http://www.ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: vmespy
--
-- author: Tristan Gingold <tristan.gingold@cern.ch>
--
-- description:
--
-- WB slave to be synthetized to test features of the vme64x core.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity vmespy is
port(
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
leds_o : out std_logic_vector(15 downto 0);
vme_write_n_i : in std_logic;
vme_lword_n_i : in std_logic;
vme_iack_n_i : in std_logic;
vme_dtack_n_i : in std_logic;
vme_ds_n_i : in std_logic_vector(1 downto 0);
vme_as_n_i : in std_logic;
vme_data_i : in std_logic_vector(31 downto 0);
vme_am_i : in std_logic_vector(5 downto 0);
vme_addr_i : in std_logic_vector(31 downto 1)
);
end vmespy;
architecture rtl of vmespy is
-- Memory map (WB byte addresses):
-- 0 - 0x3ff: sram (512*4B)
-- 0x4000: leds (4B)
-- 0x4004: last WB transaction (see the code for the format)
-- 0x4008: nbr of WB read accesses (write to clear)
-- 0x400c: nbr of WB write accesses (likewise)
-- 0x4010: nbr of write errors in pattern ram
-- 0x4014: generates bus error.
-- 0x4018: spy status
-- 0x401c: spy counters
-- 0x8000: counter (4B). Generate an interrupt when 0 is reached.
-- 0xc000: pattern ram (0x1000 * 4B)
-- 0x20000: spy ram
-- 0x40000 - 0x3ff000: pattern ram
signal counter : unsigned(31 downto 0);
signal leds : std_logic_vector(15 downto 0);
signal last_trans : std_logic_vector (28 downto 0);
signal nbr_read : unsigned (15 downto 0);
signal nbr_write: unsigned (15 downto 0);
signal nbr_write_errors: unsigned (31 downto 0);
signal pattern : std_logic_vector (31 downto 0);
type sram_type is array (0 to 16#1ff#) of std_logic_vector(31 downto 0);
signal sram: sram_type;
-- Post synchronizer signals.
signal vme_write_n : std_logic;
signal vme_lword_n : std_logic;
signal vme_iack_n : std_logic;
signal vme_dtack_n : std_logic;
signal vme_ds_n : std_logic_vector(1 downto 0);
signal vme_as_n : std_logic;
signal vme_data : std_logic_vector(31 downto 0);
signal vme_am : std_logic_vector(5 downto 0);
signal vme_addr : std_logic_vector(31 downto 1);
signal vme_as_n_d : std_logic;
-- spy state
-- Spy is enabled, waiting for trigger. Cleared when triggered.
signal spy_wait : std_logic;
-- Spy has been triggered, writing to RAM.
signal spy_write : std_logic;
-- Spy done.
signal spy_done : std_logic;
-- Number of transfers (AS rising edge before writing to RAM)
signal spy_count : unsigned(7 downto 0);
constant c_spy_depth : natural := 13;
-- Current RAM index (while writing).
signal spy_index : unsigned(c_spy_depth - 1 downto 0);
signal spy_start : std_logic;
signal spy_write_reg : std_logic;
signal spy_ram_data : std_logic_vector (75 downto 0);
begin
-- Pattern of the pattern ram.
pattern (31 downto 16) <= not slave_i.adr(15 downto 0);
pattern (15 downto 0) <= slave_i.adr(15 downto 0);
process (clk_sys_i)
procedure pattern_write
is
variable err : boolean;
begin
err := false;
for i in 3 downto 0 loop
if slave_i.sel (i) = '1'
and (slave_i.dat(8*i + 7 downto 8*i) /=
pattern (8*i + 7 downto 8*i))
then
err := true;
end if;
end loop;
if err then
nbr_write_errors <= nbr_write_errors + 1;
end if;
end pattern_write;
variable idx : natural;
variable to_ack : std_logic_vector (1 downto 0);
begin
if rising_edge(clk_sys_i) then
slave_o.ack <= '0';
slave_o.err <= '0';
if rst_n_i = '0' then
counter <= (others => '0');
leds <= (others => '0');
nbr_read <= (others => '0');
nbr_write <= (others => '0');
nbr_write_errors <= (others => '0');
spy_start <= '0';
spy_write_reg <= '0';
to_ack := (others => '0');
else
-- Decrementer
if counter /= (counter'range => '0') then
counter <= counter - 1;
end if;
spy_start <= '0';
spy_write_reg <= '0';
if slave_i.stb = '1' and slave_i.cyc = '1' then
if slave_i.adr (13 downto 12) = "00" then
-- Save transaction (very cheap scope).
last_trans (23 downto 0) <= slave_i.adr (23 downto 0);
last_trans (27 downto 24) <= slave_i.sel;
last_trans (28) <= slave_i.we;
end if;
if slave_i.we = '1' then
-- Write
nbr_write <= nbr_write + 1;
if slave_i.adr(27 downto 16) = x"000" then
case slave_i.adr (15 downto 14) is
when "00" =>
idx := to_integer(unsigned(slave_i.adr(10 downto 2)));
for i in 3 downto 0 loop
if slave_i.sel (i) = '1' then
sram(idx)(8*i + 7 downto 8*i) <=
slave_i.dat(8*i + 7 downto 8*i);
end if;
end loop;
when "01" =>
case slave_i.adr (4 downto 2) is
when "000" =>
-- leds
for i in 1 downto 0 loop
if slave_i.sel (i) = '1' then
leds(8*i + 7 downto 8*i) <=
slave_i.dat(8*i + 7 downto 8*i);
end if;
end loop;
when "001" =>
null;
when "010" =>
nbr_read <= (others => '0');
when "011" =>
nbr_write <= (others => '0');
when "100" =>
nbr_write_errors <= (others => '0');
when "101" =>
slave_o.err <= '1';
when "110" =>
spy_start <= slave_i.dat (0);
when "111" =>
spy_write_reg <= '1';
when others =>
null;
end case;
when "10" =>
for i in 3 downto 0 loop
if slave_i.sel (i) = '1' then
counter(8*i + 7 downto 8*i) <=
unsigned(slave_i.dat(8*i + 7 downto 8*i));
end if;
end loop;
when "11" =>
pattern_write;
when others =>
null;
end case;
end if;
to_ack := "01";
else
-- Read
nbr_read <= nbr_read + 1;
if slave_i.adr(27 downto 16) = x"000" then
case slave_i.adr (15 downto 14) is
when "00" =>
idx := to_integer(unsigned(slave_i.adr(10 downto 2)));
slave_o.dat <= sram(idx);
when "01" =>
case slave_i.adr (4 downto 2) is
when "000" =>
slave_o.dat(31 downto 16) <= (others => '0');
slave_o.dat(15 downto 0) <= leds;
when "001" =>
slave_o.dat <= (31 downto 29 => '0') & last_trans;
when "010" =>
slave_o.dat (31 downto 16) <= (others => '0');
slave_o.dat (15 downto 0) <= std_logic_vector (nbr_read);
when "011" =>
slave_o.dat (31 downto 16) <= (others => '0');
slave_o.dat (15 downto 0) <= std_logic_vector (nbr_write);
when "100" =>
slave_o.dat <= std_logic_vector (nbr_write_errors);
when "101" =>
slave_o.err <= '1';
when "110" =>
slave_o.dat <= (others => '0');
slave_o.dat (0) <= spy_wait;
slave_o.dat (1) <= spy_write;
slave_o.dat (2) <= spy_done;
when "111" =>
slave_o.dat <= (others => '0');
slave_o.dat (7 downto 0) <= std_logic_vector (spy_count);
slave_o.dat (16 + c_spy_depth - 1 downto 16) <= std_logic_vector (spy_index);
when others =>
null;
end case;
when "10" =>
slave_o.dat <= std_logic_vector(counter);
when "11" =>
slave_o.dat <= pattern;
when others =>
null;
end case;
to_ack := "01";
elsif slave_i.adr(27 downto 16) = x"002"
or slave_i.adr(27 downto 16) = x"003"
then
slave_o.dat <= (others => '0');
case slave_i.adr (3 downto 2) is
when "00" =>
slave_o.dat <= spy_ram_data (31 downto 0);
when "01" =>
slave_o.dat <= spy_ram_data (63 downto 32);
when "10" =>
slave_o.dat (11 downto 0) <= spy_ram_data (75 downto 64);
when others =>
null;
end case;
if to_ack = "00" then
to_ack := "10";
end if;
else
slave_o.dat <= pattern;
to_ack := "01";
end if;
end if;
end if;
end if;
slave_o.ack <= to_ack (0);
to_ack := '0' & to_ack (1);
end if;
end process;
leds_o <= leds;
int_o <= '1' when counter = 1 else '0';
-- drive unused WB slave_o outputs
slave_o.stall <= '0';
slave_o.rty <= '0';
inst_vme_write_resync: entity work.gc_sync_register
generic map (g_width => 1)
port map (clk_i => clk_sys_i,
rst_n_a_i => rst_n_i,
d_i(0) => vme_write_n_i,
q_o(0) => vme_write_n);
inst_vme_lword_resync: entity work.gc_sync_register
generic map (g_width => 1)
port map (clk_i => clk_sys_i,
rst_n_a_i => rst_n_i,
d_i(0) => vme_lword_n_i,
q_o(0) => vme_lword_n);
inst_vme_iack_resync: entity work.gc_sync_register
generic map (g_width => 1)
port map (clk_i => clk_sys_i,
rst_n_a_i => rst_n_i,
d_i(0) => vme_iack_n_i,
q_o(0) => vme_iack_n);
inst_vme_dtack_resync: entity work.gc_sync_register
generic map (g_width => 1)
port map (clk_i => clk_sys_i,
rst_n_a_i => rst_n_i,
d_i(0) => vme_dtack_n_i,
q_o(0) => vme_dtack_n);
inst_vme_ds_resync: entity work.gc_sync_register
generic map (g_width => 2)
port map (clk_i => clk_sys_i,
rst_n_a_i => rst_n_i,
d_i => vme_ds_n_i,
q_o => vme_ds_n);
inst_vme_as_resync: entity work.gc_sync_register
generic map (g_width => 1)
port map (clk_i => clk_sys_i,
rst_n_a_i => rst_n_i,
d_i(0) => vme_as_n_i,
q_o(0) => vme_as_n);
inst_vme_data_resync: entity work.gc_sync_register
generic map (g_width => 32)
port map (clk_i => clk_sys_i,
rst_n_a_i => rst_n_i,
d_i => vme_data_i,
q_o => vme_data);
inst_vme_am_resync: entity work.gc_sync_register
generic map (g_width => 6)
port map (clk_i => clk_sys_i,
rst_n_a_i => rst_n_i,
d_i => vme_am_i,
q_o => vme_am);
inst_vme_addr_resync: entity work.gc_sync_register
generic map (g_width => 31)
port map (clk_i => clk_sys_i,
rst_n_a_i => rst_n_i,
d_i => vme_addr_i,
q_o => vme_addr);
process (clk_sys_i)
type vram_type is array (0 to 2**c_spy_depth - 1) of std_logic_vector(75 downto 0);
variable vram : vram_type;
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
spy_wait <= '0';
spy_write <= '0';
spy_done <= '0';
spy_count <= (others => '0');
spy_index <= (others => '0');
vme_as_n_d <= '1';
else
-- DATA ram read.
spy_ram_data <= vram (to_integer (unsigned (slave_i.adr (c_spy_depth + 3 downto 4))));
if spy_write = '1' or spy_wait = '1' then
-- Write when writing (!) but also the current input while waiting.
vram (to_integer(spy_index)) :=
(not vme_dtack_n) & (not vme_as_n) & (not vme_iack_n) & (not vme_write_n)
& (not vme_ds_n) & vme_am
& vme_addr & (not vme_lword_n) & vme_data;
end if;
if spy_write = '1' then
-- Update memory address.
if spy_index = (spy_index'range => '1') then
spy_write <= '0';
spy_done <= '1';
else
spy_index <= spy_index + 1;
end if;
end if;
if spy_wait = '1' then
-- Trigger ?
if vme_as_n_d = '1' and vme_as_n = '0' then
if spy_count = (spy_count'range => '0') then
spy_wait <= '0';
spy_write <= '1';
spy_index <= to_unsigned(1, c_spy_depth);
else
spy_index <= (others => '0');
spy_count <= spy_count - 1;
end if;
end if;
end if;
-- Write to registers.
if spy_wait = '0' and spy_write = '0' then
if spy_write_reg = '1' then
spy_count <= unsigned (slave_i.dat (7 downto 0));
end if;
spy_wait <= spy_start;
spy_done <= spy_done and not spy_start;
end if;
-- Prev as.
vme_as_n_d <= vme_as_n;
end if;
end if;
end process;
end rtl;
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