Commit e792beed authored by Tristan Gingold's avatar Tristan Gingold

svec_base_wr: use gen_sourceid script to generate source id.

parent 6401c556
files = [
"svec_base_regs.vhd",
"svec_base_wr.vhd",
"sourceid_svec_base_pkg.vhd",
]
try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec(open("../../../" + "/general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'svec_base'})
except Exception as e:
print("Error: cannot generate source id file")
raise
......@@ -36,6 +36,7 @@ use work.wr_svec_pkg.all;
use work.buildinfo_pkg.all;
use work.wr_fabric_pkg.all;
use work.streamers_pkg.all;
use work.sourceid_svec_base_pkg;
library unisim;
use unisim.vcomponents.all;
......@@ -653,9 +654,18 @@ begin -- architecture top
when x"3" =>
-- BOM
metadata_data <= x"fffe0000";
when x"4" | x"5" | x"6" | x"7" =>
when x"4" =>
-- source id
metadata_data <= x"00000000";
metadata_data <= sourceid_svec_base_pkg.sourceid(127 downto 96);
when x"5" =>
-- source id
metadata_data <= sourceid_svec_base_pkg.sourceid(95 downto 64);
when x"6" =>
-- source id
metadata_data <= sourceid_svec_base_pkg.sourceid(63 downto 32);
when x"7" =>
-- source id
metadata_data <= sourceid_svec_base_pkg.sourceid(31 downto 0);
when x"8" =>
-- capability mask
metadata_data <= x"00000000";
......
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