Commit f95e8aa0 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

intitial commit (SVEC application FPGA bootloader)

parent d74b6b17
*~
*#
fifo_generator_v6_1
testbench/svec_sfpga_top/sample_bitstream/
*.*\#
\#*
.\#*
*.*~
syn/
work
*.wlf
modelsim.ini
transcript
*.vstf
*.bak
*.vcd
*.h
doc/
*.o
*.bin
*.elf
Makefile
\ No newline at end of file
files =["chipscope_icon.ngc", "chipscope_ila.ngc" ]
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files = ["mini_vme.vhd"];
-- minimalistic VME core providing only CR/CSR accesses. For SVEC AFPGA bootup
-- purposes.
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
entity xmini_vme is
generic (
g_user_csr_start : unsigned(20 downto 0);
g_user_csr_end : unsigned(20 downto 0));
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- "Passive" mode enable: when '1', the core never touches the bus
passive_i : in std_logic;
-- stripped-down VME I/O
VME_RST_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_LWORD_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0); -- Geographical Address and GA parity
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in
);
end xmini_vme;
architecture rtl of xmini_vme is
constant c_AM_CS_CSR : std_logic_vector(5 downto 0) := "101111";
constant c_DTACK_LENGTH : integer := 20;
signal as_synced, ds_synced : std_logic;
signal ds_a, as_p1, ds_p1, write_n : std_logic;
signal lword_latched : std_logic;
signal addr_latched : std_logic_vector(31 downto 1);
signal readback_data, data_latched : std_logic_vector(31 downto 0);
signal am_latched : std_logic_vector(5 downto 0);
signal ds_latched : std_logic_vector(1 downto 0);
signal ga_latched : std_logic_vector(5 downto 0);
signal addr_valid, data_valid, ga_parity_ok : std_logic;
type t_fsm_state is (IDLE, DECODE_ADDR, EXEC_CYCLE, WAIT_ACK, DTACK);
signal state : t_fsm_state;
signal am_match, addr_match, dtype_match : std_logic;
signal is_write : std_logic;
signal dtack_counter : unsigned(7 downto 0);
begin -- rtl
U_Sync_AS : gc_sync_ffs
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
data_i => VME_AS_n_i,
npulse_o => as_p1,
synced_o => as_synced);
ds_a <= VME_DS_n_i(0) and VME_DS_n_i(1);
U_Sync_DS : gc_sync_ffs
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
data_i => ds_a,
npulse_o => ds_p1,
synced_o => ds_synced);
U_Sync_Write : gc_sync_ffs
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
data_i => VME_WRITE_n_i,
synced_o => write_n);
ga_parity_ok <= ga_latched(5) xor ga_latched(4) xor ga_latched(3) xor ga_latched(2) xor ga_latched(1) xor ga_latched(0);
p_latch_addr : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(rst_n_i = '0') then
addr_valid <= '0';
elsif(as_p1 = '1') then
addr_latched <= VME_ADDR_i;
addr_valid <= '1';
am_latched <= VME_AM_i;
ga_latched <= VME_GA_i;
lword_latched <= VME_LWORD_n_i;
elsif(as_synced = '1') then
addr_valid <= '0';
end if;
end if;
end process;
p_latch_data : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
data_valid <= '0';
elsif(ds_p1 = '1') then
data_latched <= VME_DATA_b_i;
ds_latched <= VME_DS_n_i;
data_valid <= '1';
elsif(ds_synced = '1') then
data_valid <= '0';
end if;
end if;
end process;
p_decode : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
am_match <= '0';
addr_match <= '0';
dtype_match <= '0';
else
-- we accept only CS/CSR accesses
if(am_latched = c_AM_CS_CSR) then
am_match <= '1';
else
am_match <= '0';
end if;
-- ... D32 data type
if(ds_latched = "00" and lword_latched = '0' and addr_latched(1) = '0') then
dtype_match <= '1';
else
dtype_match <= '0';
end if;
-- ... and address matches our supported range
if(ga_parity_ok = '1' and addr_latched(23 downto 19) = not ga_latched(4 downto 0) and addr_latched(31 downto 24) = x"00") then
addr_match <= '1';
else
addr_match <= '0';
end if;
end if;
end if;
end process;
p_fsm : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_i = '0' then
state <= IDLE;
VME_DATA_DIR_o <= '0';
VME_DATA_OE_N_o <= '0';
VME_DTACK_n_o <= '0';
VME_DTACK_OE_o <= '0';
else
case state is
when IDLE =>
VME_DATA_DIR_o <= '0';
VME_DTACK_n_o <= '1';
VME_DTACK_OE_o <= '0';
dtack_counter <= (others => '0');
if(addr_valid = '1' and data_valid = '1') then
state <= DECODE_ADDR;
end if;
when DECODE_ADDR =>
if(addr_valid = '1') then
if(addr_match = '1' and am_match = '1' and dtype_match = '1') then
if((unsigned(addr_latched(18 downto 2)) & "00") >= g_user_csr_start
and (unsigned(addr_latched(18 downto 2)) & "00") <= g_user_csr_end) then
state <= EXEC_CYCLE;
is_write <= not write_n;
end if;
else
state <= IDLE;
end if;
end if;
when EXEC_CYCLE =>
master_o.adr <= std_logic_vector(resize(((unsigned(addr_latched(18 downto 2)) & "00") - g_user_csr_start), c_wishbone_address_width));
master_o.dat <= data_latched;
master_o.cyc <= '1';
master_o.sel <= "1111";
master_o.stb <= '1';
master_o.we <= is_write;
state <= WAIT_ACK;
when WAIT_ACK =>
if(master_i.stall = '0') then
master_o.stb <= '0';
end if;
if(master_i.ack = '1') then
state <= DTACK;
readback_data <= master_i.dat;
elsif(ds_synced = '1') then
state <= IDLE;
end if;
when DTACK =>
VME_DATA_b_o <= readback_data;
if(passive_i = '1') then
VME_DATA_DIR_o <= '0';
VME_DATA_DIR_o <= '0';
VME_DTACK_OE_o <= '0';
else
VME_DTACK_n_o <= '0';
VME_DTACK_OE_o <= '1';
VME_DATA_DIR_o <= not is_write;
end if;
dtack_counter <= dtack_counter + 1;
if(ds_synced = '1') then
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
end rtl;
`define ADDR_XLDR_CSR 5'h0
`define XLDR_CSR_START_OFFSET 0
`define XLDR_CSR_START 32'h00000001
`define XLDR_CSR_DONE_OFFSET 1
`define XLDR_CSR_DONE 32'h00000002
`define XLDR_CSR_ERROR_OFFSET 2
`define XLDR_CSR_ERROR 32'h00000004
`define XLDR_CSR_BUSY_OFFSET 3
`define XLDR_CSR_BUSY 32'h00000008
`define XLDR_CSR_MSBF_OFFSET 4
`define XLDR_CSR_MSBF 32'h00000010
`define XLDR_CSR_SWRST_OFFSET 5
`define XLDR_CSR_SWRST 32'h00000020
`define XLDR_CSR_EXIT_OFFSET 6
`define XLDR_CSR_EXIT 32'h00000040
`define XLDR_CSR_CLKDIV_OFFSET 8
`define XLDR_CSR_CLKDIV 32'h00003f00
`define ADDR_XLDR_BTRIGR 5'h4
`define ADDR_XLDR_GPIOR 5'h8
`define ADDR_XLDR_FIFO_R0 5'hc
`define XLDR_FIFO_R0_XSIZE_OFFSET 0
`define XLDR_FIFO_R0_XSIZE 32'h00000003
`define XLDR_FIFO_R0_XLAST_OFFSET 2
`define XLDR_FIFO_R0_XLAST 32'h00000004
`define ADDR_XLDR_FIFO_R1 5'h10
`define XLDR_FIFO_R1_XDATA_OFFSET 0
`define XLDR_FIFO_R1_XDATA 32'hffffffff
`define ADDR_XLDR_FIFO_CSR 5'h14
`define XLDR_FIFO_CSR_FULL_OFFSET 16
`define XLDR_FIFO_CSR_FULL 32'h00010000
`define XLDR_FIFO_CSR_EMPTY_OFFSET 17
`define XLDR_FIFO_CSR_EMPTY 32'h00020000
`define XLDR_FIFO_CSR_USEDW_OFFSET 0
`define XLDR_FIFO_CSR_USEDW 32'h000000ff
`timescale 1ns/1ns
module sn74vmeh22501 (
input oeab1,
oeby1_n,
a1,
output y1,
inout b1,
input oeab2,
oeby2_n,
a2,
output y2,
inout b2,
input oe_n,
input dir,
clkab,
le,
clkba,
inout [1:8] a3,
inout [1:8] b3);
assign b1 = oeab1 ? a1 : 1'bz;
assign y1 = oeby1_n ? 1'bz : b1;
assign b2 = oeab2 ? a2 : 1'bz;
assign y2 = oeby2_n ? 1'bz : b2;
reg [1:8] b3LFF;
always @(posedge clkab) if (~le) b3LFF <= #1 a3;
always @* if (le) b3LFF = a3;
assign b3 = (~oe_n && dir) ? b3LFF : 8'hz;
reg [1:8] a3LFF;
always @(posedge clkba) if (~le) a3LFF <= #1 b3;
always @* if (le) a3LFF = b3;
assign a3 = (~oe_n && ~dir) ? a3LFF : 8'hz;
endmodule
`include "components/sn74vmeh22501.v"
`include "vme64x_bfm.svh"
module bidir_buf(
a,
b,
dir, /* 0: a->b, 1: b->a */
oe_n );
parameter g_width = 1;
inout [g_width-1:0] a,b;
input dir, oe_n;
assign b = (!dir && !oe_n) ? a : 'bz;
assign a = (dir && !oe_n) ? b : 'bz;
endmodule // bidir_buf
module svec_vme_buffers (
output VME_AS_n_o,
output VME_RST_n_o,
output VME_WRITE_n_o,
output [5:0] VME_AM_o,
output [1:0] VME_DS_n_o,
output [5:0] VME_GA_o,
input VME_BERR_i,
input VME_DTACK_n_i,
input VME_RETRY_n_i,
input VME_RETRY_OE_i,
inout VME_LWORD_n_b,
inout [31:1] VME_ADDR_b,
inout [31:0] VME_DATA_b,
output VME_BBSY_n_o,
input [6:0] VME_IRQ_n_i,
output VME_IACKIN_n_o,
input VME_IACKOUT_n_i,
output VME_IACK_n_o,
input VME_DTACK_OE_i,
input VME_DATA_DIR_i,
input VME_DATA_OE_N_i,
input VME_ADDR_DIR_i,
input VME_ADDR_OE_N_i,
IVME64X.slave slave
);
pullup(slave.as_n);
pullup(slave.rst_n);
pullup(slave.irq_n[0]);
pullup(slave.irq_n[1]);
pullup(slave.irq_n[2]);
pullup(slave.irq_n[3]);
pullup(slave.irq_n[4]);
pullup(slave.irq_n[5]);
pullup(slave.irq_n[6]);
pullup(slave.iack_n);
pullup(slave.dtack_n);
pullup(slave.retry_n);
pullup(slave.ds_n[1]);
pullup(slave.ds_n[0]);
pullup(slave.lword_n);
pullup(slave.berr_n);
pullup(slave.write_n);
pulldown(slave.bbsy_n);
pullup(slave.iackin_n);
assign VME_RST_n_o = slave.rst_n;
assign VME_AS_n_o = slave.as_n;
assign VME_GA_o = slave.ga;
assign VME_WRITE_n_o = slave.write_n;
assign VME_AM_o = slave.am;
assign VME_DS_n_o = slave.ds_n;
assign VME_BBSY_n_o = slave.bbsy_n;
assign VME_IACKIN_n_o = slave.iackin_n;
assign VME_IACK_n_o = slave.iack_n;
bidir_buf #(1) b0 (slave.lword_n, VME_LWORD_n_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
bidir_buf #(31) b1 (slave.addr, VME_ADDR_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
bidir_buf #(33) b2 (slave.data, VME_DATA_b, VME_DATA_DIR_i, VME_DATA_OE_N_i);
pulldown(VME_BERR_i);
pulldown(VME_ADDR_DIR_i);
pulldown(VME_ADDR_OE_N_i);
pulldown(VME_DATA_DIR_i);
pulldown(VME_DATA_OE_N_i);
assign slave.dtack_n = VME_DTACK_n_i;
assign slave.berr_n = ~VME_BERR_i;
assign slave.retry_n = VME_RETRY_n_i;
endmodule
`define DECLARE_VME_BUFFERS(iface) \
wire VME_AS_n;\
wire VME_RST_n;\
wire VME_WRITE_n;\
wire [5:0] VME_AM;\
wire [1:0] VME_DS_n;\
wire VME_BERR;\
wire VME_DTACK_n;\
wire VME_RETRY_n;\
wire VME_RETRY_OE;\
wire VME_LWORD_n;\
wire [31:1]VME_ADDR;\
wire [31:0]VME_DATA;\
wire VME_BBSY_n;\
wire [6:0]VME_IRQ_n;\
wire VME_IACKIN_n,VME_IACK_n;\
wire VME_IACKOUT_n;\
wire VME_DTACK_OE;\
wire VME_DATA_DIR;\
wire VME_DATA_OE_N;\
wire VME_ADDR_DIR;\
wire VME_ADDR_OE_N;\
svec_vme_buffers U_VME_Bufs ( \
.VME_AS_n_o(VME_AS_n),\
.VME_RST_n_o(VME_RST_n),\
.VME_WRITE_n_o(VME_WRITE_n),\
.VME_AM_o(VME_AM),\
.VME_DS_n_o(VME_DS_n),\
.VME_BERR_i(VME_BERR),\
.VME_DTACK_n_i(VME_DTACK_n),\
.VME_RETRY_n_i(VME_RETRY_n),\
.VME_RETRY_OE_i(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_BBSY_n_o(VME_BBSY_n),\
.VME_IRQ_n_i(VME_IRQ_n),\
.VME_IACK_n_o(VME_IACK_n),\
.VME_IACKIN_n_o(VME_IACKIN_n),\
.VME_IACKOUT_n_i(VME_IACKOUT_n),\
.VME_DTACK_OE_i(VME_DTACK_OE),\
.VME_DATA_DIR_i(VME_DATA_DIR),\
.VME_DATA_OE_N_i(VME_DATA_OE_N),\
.VME_ADDR_DIR_i(VME_ADDR_DIR),\
.VME_ADDR_OE_N_i(VME_ADDR_OE_N),\
.slave(iface)\
);
function automatic bit[5:0] _gen_ga(int slot);
bit[4:0] slot_id = slot;
return {^slot_id, ~slot_id};
endfunction // _gen_ga
`define WIRE_VME_PINS(slot_id) \
.VME_AS_n_i(VME_AS_n),\
.VME_RST_n_i(VME_RST_n),\
.VME_WRITE_n_i(VME_WRITE_n),\
.VME_AM_i(VME_AM),\
.VME_DS_n_i(VME_DS_n),\
.VME_GA_i(_gen_ga(slot_id)),\
.VME_BERR_o(VME_BERR),\
.VME_DTACK_n_o(VME_DTACK_n),\
.VME_RETRY_n_o(VME_RETRY_n),\
.VME_RETRY_OE_o(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_BBSY_n_i(VME_BBSY_n),\
.VME_IRQ_n_o(VME_IRQ_n),\
.VME_IACK_n_i(VME_IACK_n),\
.VME_IACKIN_n_i(VME_IACKIN_n),\
.VME_IACKOUT_n_o(VME_IACKOUT_n),\
.VME_DTACK_OE_o(VME_DTACK_OE),\
.VME_DATA_DIR_o(VME_DATA_DIR),\
.VME_DATA_OE_N_o(VME_DATA_OE_N),\
.VME_ADDR_DIR_o(VME_ADDR_DIR),\
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
\ No newline at end of file
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target = "xilinx"
action = "synthesis"
fetchto = "../../../ip_cores"
syn_device = "xc6slx9"
syn_grade = "-2"
syn_package = "ftg256"
syn_top = "svec_sfpga_top"
syn_project = "svec_sfpga.xise"
modules = { "local" : [ "../../top/svec_sfpga", "../../platform" ] }
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action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim/vme64x_bfm +incdir+../../sim/wb"
files = [ "main.sv", "glbl.v", "SIM_CONFIG_S6_SERIAL.v" ]
modules = { "local" : [ "../../top/svec_sfpga" ] }
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// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
`include "regs/xloader_regs.vh"
module main;
reg rst_n = 0;
reg clk_20m = 0;
wire cclk, din, program_b, init_b, done, suspend;
wire [1:0] m;
always #25ns clk_20m <= ~clk_20m;
initial begin
repeat(20) @(posedge clk_20m);
rst_n = 1;
end
IVME64X VME(rst_n);
`DECLARE_VME_BUFFERS(VME.slave);
svec_sfpga_top
DUT (
.lclk_n_i(clk_20m),
.rst_n_i(rst_n),
`WIRE_VME_PINS(8),
.boot_clk_o(cclk),
.boot_config_o(program_b),
.boot_status_i(init_b),
.boot_done_i(done),
.boot_dout_o(din)
);
SIM_CONFIG_S6_SERIAL2
#(
.DEVICE_ID(32'h34000093) // 6slx150t
) U_serial_sim
(
.DONE(done),
.CCLK(cclk),
.DIN(din),
.INITB(init_b),
.M(2'b11),
.PROGB(program_b)
);
class CSimDrv_Xloader;
protected CBusAccessor_VME64x acc;
protected uint64_t base;
function new(CBusAccessor_VME64x _acc, uint64_t _base);
acc = _acc;
base = _base;
endfunction
task enter_boot_mode();
int i;
const int boot_seq[8] = '{'hde, 'had, 'hbe, 'hef, 'hca, 'hfe, 'hba, 'hbe};
for(i=0;i<8;i++)
acc.write(base + `ADDR_XLDR_BTRIGR, boot_seq[i]);
endtask // enter_boot_mode
task load_bitstream(string filename);
int f,i, pos=0;
uint64_t csr;
acc.write(base + `ADDR_XLDR_CSR, `XLDR_CSR_SWRST );
acc.write(base + `ADDR_XLDR_CSR, `XLDR_CSR_START | `XLDR_CSR_MSBF);
f = $fopen(filename, "r");
while(!$feof(f))
begin
uint64_t r,r2;
acc.read(base + `ADDR_XLDR_FIFO_CSR, r);
if(!(r&`XLDR_FIFO_CSR_FULL)) begin
int n;
int x;
n = $fread(x, f);
pos+=n;
if((pos % 4000) == 0)
$display("%d bytes sent", pos);
r=x;
r2=(n - 1) | ($feof(f) ? `XLDR_FIFO_R0_XLAST : 0);
acc.write(base +`ADDR_XLDR_FIFO_R0, r2);
acc.write(base +`ADDR_XLDR_FIFO_R1, r);
end
end
$fclose(f);
while(1) begin
acc.read (base + `ADDR_XLDR_CSR, csr);
if(csr & `XLDR_CSR_DONE) begin
$display("Bitstream loaded, status: %s", (csr & `XLDR_CSR_ERROR ? "ERROR" : "OK"));
acc.write(base + `ADDR_XLDR_CSR, `XLDR_CSR_EXIT);
return;
end
end
endtask
endclass
initial begin
uint64_t d;
int i, result;
CBusAccessor_VME64x acc = new(VME.master);
CSimDrv_Xloader drv;
#10us;
acc.set_default_modifiers(A32 | CR_CSR | D32);
// acc.write('h70000 + `ADDR_XLDR_GPIOR, 'haa);
drv = new(acc, 'h70000);
#100us;
drv.enter_boot_mode();
#100us;
drv.load_bitstream("sample_bitstream/crc_gen.bin");
end
endmodule // main
vlog -sv main.sv +incdir+. +incdir+../../sim/wb +incdir+../../sim/vme64x_bfm +incdir+../../sim
vsim work.main -voptargs=+acc
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
run 30us
\ No newline at end of file
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/g_interface_mode
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/g_address_granularity
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/clk_sys_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/rst_n_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_cyc_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_stb_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_we_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_adr_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_sel_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_dat_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_dat_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_ack_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_stall_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_cclk_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_din_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_program_b_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_init_b_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_done_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_suspend_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/xlx_m_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/boot_trig_p1_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/boot_exit_p1_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/boot_en_i
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/gpio_o
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/state
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/clk_div
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/tick
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/init_b_synced
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/done_synced
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/timeout_counter
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_in
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/wb_out
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/regs_in
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/regs_out
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/d_data
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/d_size
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/d_last
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/bit_counter
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/boot_state
add wave -noupdate -radix hexadecimal /main/DUT/U_Xilinx_Loader/U_Wrapped_XLDR/startup_count
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {123219856 ps} 0}
configure wave -namecolwidth 177
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {282492928 ps}
files = [ "svec_sfpga_top.vhd", "svec_sfpga_top.ucf" ]
fetchto = "../../ip_cores"
modules = {
"local" : ["../../rtl" ],
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git" ]
}
#===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = B1;
NET "vme_rst_n_i" LOC = G6;
NET "vme_retry_oe_o" LOC = D3;
NET "vme_retry_n_o" LOC = D1;
NET "vme_lword_n_b" LOC = B3;
NET "vme_iackout_n_o" LOC = E4;
NET "vme_iackin_n_i" LOC = F6;
NET "vme_iack_n_i" LOC = E3;
NET "vme_dtack_oe_o" LOC = C3;
NET "vme_dtack_n_o" LOC = C2;
NET "vme_ds_n_i[1]" LOC = N9;
NET "vme_ds_n_i[0]" LOC = P9;
NET "vme_data_oe_n_o" LOC = K6;
NET "vme_data_dir_o" LOC = F4;
NET "vme_berr_o" LOC = C1;
NET "vme_as_n_i" LOC = F5;
NET "vme_addr_oe_n_o" LOC = K5;
NET "vme_addr_dir_o" LOC = B2;
NET "vme_irq_n_o[6]" LOC = C11;
NET "vme_irq_n_o[5]" LOC = C8;
NET "vme_irq_n_o[4]" LOC = D8;
NET "vme_irq_n_o[3]" LOC = C10;
NET "vme_irq_n_o[2]" LOC = E10;
NET "vme_irq_n_o[1]" LOC = E8;
NET "vme_irq_n_o[0]" LOC = E7;
NET "vme_ga_i[5]" LOC = A3;
NET "vme_ga_i[4]" LOC = A10;
NET "vme_ga_i[3]" LOC = B10;
NET "vme_ga_i[2]" LOC = A9;
NET "vme_ga_i[1]" LOC = C9;
NET "vme_ga_i[0]" LOC = A8;
NET "vme_data_b[31]" LOC = F7;
NET "vme_data_b[30]" LOC = A6;
NET "vme_data_b[29]" LOC = B6;
NET "vme_data_b[28]" LOC = C5;
NET "vme_data_b[27]" LOC = D5;
NET "vme_data_b[26]" LOC = A5;
NET "vme_data_b[25]" LOC = B5;
NET "vme_data_b[24]" LOC = A4;
NET "vme_data_b[23]" LOC = T8;
NET "vme_data_b[22]" LOC = P8;
NET "vme_data_b[21]" LOC = N8;
NET "vme_data_b[20]" LOC = M9;
NET "vme_data_b[19]" LOC = T9;
NET "vme_data_b[18]" LOC = R9;
NET "vme_data_b[17]" LOC = M10;
NET "vme_data_b[16]" LOC = L10;
NET "vme_data_b[15]" LOC = N6;
NET "vme_data_b[14]" LOC = M6;
NET "vme_data_b[13]" LOC = T4;
NET "vme_data_b[12]" LOC = P4;
NET "vme_data_b[11]" LOC = L7;
NET "vme_data_b[10]" LOC = L8;
NET "vme_data_b[9]" LOC = P5;
NET "vme_data_b[8]" LOC = N5;
NET "vme_data_b[7]" LOC = T5;
NET "vme_data_b[6]" LOC = R5;
NET "vme_data_b[5]" LOC = T6;
NET "vme_data_b[4]" LOC = P6;
NET "vme_data_b[3]" LOC = T7;
NET "vme_data_b[2]" LOC = R7;
NET "vme_data_b[1]" LOC = M7;
NET "vme_data_b[0]" LOC = P7;
NET "vme_am_i[5]" LOC = B8;
NET "vme_am_i[4]" LOC = C6;
NET "vme_am_i[3]" LOC = D6;
NET "vme_am_i[2]" LOC = A7;
NET "vme_am_i[1]" LOC = C7;
NET "vme_am_i[0]" LOC = E6;
NET "vme_addr_b[31]" LOC = E1;
NET "vme_addr_b[30]" LOC = E2;
NET "vme_addr_b[29]" LOC = L5;
NET "vme_addr_b[28]" LOC = L4;
NET "vme_addr_b[27]" LOC = H3;
NET "vme_addr_b[26]" LOC = J4;
NET "vme_addr_b[25]" LOC = K3;
NET "vme_addr_b[24]" LOC = F1;
NET "vme_addr_b[23]" LOC = F2;
NET "vme_addr_b[22]" LOC = G1;
NET "vme_addr_b[21]" LOC = G3;
NET "vme_addr_b[20]" LOC = H1;
NET "vme_addr_b[19]" LOC = H2;
NET "vme_addr_b[18]" LOC = J1;
NET "vme_addr_b[17]" LOC = J3;
NET "vme_addr_b[16]" LOC = K1;
NET "vme_addr_b[15]" LOC = K2;
NET "vme_addr_b[14]" LOC = L1;
NET "vme_addr_b[13]" LOC = L3;
NET "vme_addr_b[12]" LOC = M1;
NET "vme_addr_b[11]" LOC = M2;
NET "vme_addr_b[10]" LOC = N1;
NET "vme_addr_b[9]" LOC = N3;
NET "vme_addr_b[8]" LOC = P1;
NET "vme_addr_b[7]" LOC = P2;
NET "vme_addr_b[6]" LOC = R1;
NET "vme_addr_b[5]" LOC = R2;
NET "vme_addr_b[4]" LOC = N4;
NET "vme_addr_b[3]" LOC = M5;
NET "vme_addr_b[2]" LOC = M3;
NET "vme_addr_b[1]" LOC = M4;
#----------------------------------------
# Application FPGA boot control
#----------------------------------------
NET "boot_clk_o" LOC = F14;
NET "boot_config_o" LOC = C15;
NET "boot_done_i" LOC = C16;
NET "boot_dout_o" LOC = F13;
NET "boot_status_i" LOC = E16;
NET "debugled_o[2]" LOC = P15;
NET "debugled_o[1]" LOC = L16;
#IO standards
NET "vme_write_n_i" IOSTANDARD="LVCMOS33";
NET "vme_rst_n_i" IOSTANDARD="LVCMOS33";
NET "vme_retry_oe_o" IOSTANDARD="LVCMOS33";
NET "vme_retry_n_o" IOSTANDARD="LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD="LVCMOS33";
NET "vme_iackout_n_o" IOSTANDARD="LVCMOS33";
NET "vme_iackin_n_i" IOSTANDARD="LVCMOS33";
NET "vme_iack_n_i" IOSTANDARD="LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD="LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD="LVCMOS33";
NET "vme_ds_n_i[1]" IOSTANDARD="LVCMOS33";
NET "vme_ds_n_i[0]" IOSTANDARD="LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD="LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD="LVCMOS33";
NET "vme_berr_o" IOSTANDARD="LVCMOS33";
NET "vme_as_n_i" IOSTANDARD="LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD="LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[6]" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[5]" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[4]" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[3]" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[2]" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[1]" IOSTANDARD="LVCMOS33";
NET "vme_irq_n_o[0]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[5]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[1]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[0]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[31]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[30]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[29]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[28]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[27]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[26]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[25]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[24]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[23]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[22]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[21]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[20]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[19]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[18]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[17]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[16]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[15]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[14]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[13]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[12]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[11]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[10]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[9]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[8]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[7]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[6]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[5]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[4]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[3]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[2]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[1]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[0]" IOSTANDARD="LVCMOS33";
NET "vme_am_i[5]" IOSTANDARD="LVCMOS33";
NET "vme_am_i[4]" IOSTANDARD="LVCMOS33";
NET "vme_am_i[3]" IOSTANDARD="LVCMOS33";
NET "vme_am_i[2]" IOSTANDARD="LVCMOS33";
NET "vme_am_i[1]" IOSTANDARD="LVCMOS33";
NET "vme_am_i[0]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[31]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[30]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[29]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[28]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[27]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[26]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[25]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[24]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[23]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[22]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[21]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[20]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[19]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[18]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[17]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[16]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[15]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[14]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[13]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[12]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[11]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[10]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[9]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[8]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[7]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[6]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[5]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[4]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[3]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[2]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[1]" IOSTANDARD="LVCMOS33";
#----------------------------------------
# Application FPGA boot control
#----------------------------------------
NET "boot_clk_o" IOSTANDARD="LVCMOS33";
NET "boot_config_o" IOSTANDARD="LVCMOS33";
NET "boot_done_i" IOSTANDARD="LVCMOS33";
NET "boot_dout_o" IOSTANDARD="LVCMOS33";
NET "boot_status_i" IOSTANDARD="LVCMOS33";
NET "debugled_o[2]" IOSTANDARD="LVCMOS33";
NET "debugled_o[1]" IOSTANDARD="LVCMOS33";
# Clocks/resets
NET "rst_n_i" LOC = E15;
NET "lclk_n_i" LOC = H5;
NET "rst_n_i" IOSTANDARD="LVCMOS33";
NET "lclk_n_i" IOSTANDARD="LVCMOS33";
\ No newline at end of file
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