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v1.5.0 1.5.0 - 2020-11-02 =================== Added ----- - sw: add SPI flash partitions - hdl: enable DDR4 Changed ------- - sw: internal driver improvements
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v1.5.1 1.5.1 - 2020-11-24 ================== Fixed ----- - sw: NULL pointer at load time when using the SPI controller - sw: remove old unload procedure that causes BUG_ON to be triggered without valid reasons
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v1.5.2 1.5.2 - 2020-11-24 ================== Added ----- - sw: tool to inspect SVEC bitstream ROM Fixed ----- - hdl: svec-base version
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v2.0.1 2.0.1 - 2021-02-08 ================== Added ----- - sw: dynamically set the compatibility version between software and FPGA - sw: added the possibility to ignore the version check Changed ------- - hdl: the DMA interface changed to support BLT and MBLT acquisitions
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v2.0.2 2.0.2 - 2021-03-16 ================== Changed ------- - sw: better version validation implementation
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v2.0.3 2.0.3 - 2021-03-22 ================== Fixed ----- - sw: fix SVEC flasher size
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v2.0.4 2.0.4 - 2021-07-29 ================== Fixed ----- - sw: improve compatibility with newer ( > 3.10) Linux kernel version
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v3.0.0 3.0.0 - 2022-12-05 ================== Added ----- - ci: better automation - sw: support for Linux 5.10 Removed ------- - hdl: unused and obsolete top-levels and simulations - hdl: Xilinx chipscope for SFPGA (files were actually for AFPGA) Changed ------- - hdl: 'golden_wr' top-level renamed to 'wr_example' - hdl: 'template' testbench now used for simulating the golden top-level - sw|API change: the API to flash a bitstream moved from debugfs to sysfs. The Linux kernel community removed API we used. The same behavior was achievable only using sysfs. - bld: improved Makefiles Fixed ----- - hdl: building of all top-levels - hdl: missing ddr and wr-cores dependencies - hdl: corrected and re-enabled timing constraints - hdl: location of general-cores in rtl Manifest
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