Simple VME FMC Carrier (SVEC)
Project description
The FMC VME Carrier is an FMC carrier that can hold two FMC cards and an SFP connector. The FMC mezzanine slots use low-pin count (LPC) connectors. This board is optimised for cost and will be usable with most of the FMC cards designed within the OHR project (e.g. ADC cards, Fine Delay). For boards needing more possibilities (e.g. programmable clock resources, fast SRAM, fast interconnect between carriers), the VME FMC Carrier - VFC can be used.
Other FMC projects and the FMC standard are described in FMC Projects.
svec4_res.jpg
SVEC final component placement*
Main Features
- VME64x interface
- VME P2 connector provides access to a Rear Transition Module (compatible to VFC)
- 2 Low-pin count FMC slots
o Vadj fixed to 2.5V
o No dedicated clock signals from Carrier to FMC (as only available on HPC pins and use LPC)
o FMC connectivity: all 34 differential pairs connected, 1 GTP transceiver with clock, 2 clock pairs, JTAG - Main FPGA: Spartan-6 XC6SLX150T-FGG900
- Auxilary (bootup/PLL config) FPGA
o XC6SLX9-2FTG256C
o Provides VME bootloader, early oscillator/PLL config - Clocking
o 1x 10-280 MHz I2C Programmable XO Oscillator Silicon Labs Si570 (for general purpose use)
o 1x 25 MHz VCTCXO (White Rabbit oscillator)
o 1x 20 MHz VCXO (White Rabbit oscillator)
o Main synthesizer/fanout: 2x CDCM61004RHBT - On-board memories
o 2x 256 MB DDR3 (16-bit bus)
o 1x 128 Mb SPI flash for FPGA firmware storage
o 1x I2C configuration EEPROM (24LC64) - Front panel
o 1x SFP port (White Rabbit-compatible)
o 4x LEMO/SMC programmable I/Os capable of driving 3.3V @ 50 ohm
o 2x eSATA connectors (1 - straight, 2 - crossover)
o 8x Programmable LED
o 1x miniUSB connector (USB 2.0)
o reset push button - Internal connectors
o Xilinx-style JTAG
o VME64x, with some P2 lines going to the main FPGA
o optional internal USB 2.0 High Speed connector for stand-alone applications
o optional 2 x SATA connector for stand-alone PCI Express connectivity (clock + data)
o optional 4 UFL connectors with low-jitter clock for FMC cards - FPGA configuration
o from SPI flash or via VME - Stand-alone features (optional)
o External supply connector (3.3V, 5V) on internal SATA connector
o PCIe interface on internal SATA connector - 10-layer PCB
Project information
- Official production documentation:
- Users
Contacts
General question about project
- Erik van der Bij - CERN
Status
| Date| * Event *|
| 01-07-2011 | First ideas for starting this simpler and cheaper version
of the FMC VME Carrier.
|
| 19-07-2011 | Main features specification written. |
| 10-08-2011 | Project on hold as no resources available. |
| 25-10-2011 | Order sent out to a company for the schematics design.
|
| 10-11-2011 | Schematics design under way. Expect a version to review
by end November December January. |
| 17-01-2012 | Expect schematics for review on 25 January. |
| 25-01-2012 | Received schematics for review. |
| 01-02-2012 | Schematics design review held.
review01022012 |
| 06-02-2012 | Comments received on review.
review01022012comments |
| 09-02-2012 | Schematics available for new review. Second review
planned for 15-02-2012 |
| 15-02-2012 | Skipping second review for lack of resources. Launch PCB
design. |
| 28-02-2012 | First component placement made. |
| 12-03-2012 | 30% of the routing is done. 26 March first layout ready
for review. |
| 02-04-2012 | Review will be held on 3 April. pdf files in the Files
area, rest in the
Repository.
|
| 03-04-2012 | Review held (schematics + PCB layout)
review03042012. Designer will come to CERN. |
| 25-04-2012 | Review held (schematics + PCB layout)
review25042012. |
| 27-04-2012 | Comments received on review
review25042012comments. |
| 27-04-2012 | Reviewed comments on review
review27042012. |
| 02-05-2012 | Final files created. Ordered 4 assembled boards. |
| 29-05-2012 | Schematics clean-up, changelog
Erik van der Bij, Matthieu Cattin, Tomasz Wlostowski - 2 May 2012