Frequently Asked Questions
Hardware
Firmware
Q: Is the FPGA programmable from the JTAG header on the board?
A: Yes, both FPGAs are programmable from the JTAG header on the board. After powering down you will loose the configuration.
With this same JTAG header you can also program the Configuration EEPROM that is connected to the "system FPGA", so that the "system FPGA" can start up with the firmware that is preloaded into the EEPROM. Currently it is not possible to also load the "Application FPGA" from this EEPROM. It would require a specific firmware to be written and loaded in the "System FPGA".
Actually the board will be delivered with the "system FPGA" EEPROM pre-loaded with a VME bus interface (the bootloader). With a program writing over the VME bus one is able to program the "application FPGA" who would then take over the control of the VME bus and disable the "system FPGA".
- Schematics at Project information -> Official production documentation.
- Software using the bootloader
Q: Is there a FPGA reference design available?
A: We have not yet a fully documented reference design. However, the "Golden bitstream" is a good start. This is the code that will be loaded in the "application FPGA" and that is able to read the I2C bus on the mezzanines. For the "system FPGA" you may look at the bootloader
- Golden bitstream manual
- VHDL code Golden version
- VHDL code bootloader
- All code at the SVEC Repository.
Q: What version of the Xilinx tools are you using?
A: We use Xilinx ISE. Currently versions 13.3 and 14.1 are working fine.
Erik van der Bij, Tom Wlostowski, Matthieu Cattin - 20 December 2012